STCN75M2E STMicroelectronics, STCN75M2E Datasheet - Page 20

• Manufacturer Part Number: STCN75M2E
• Description: IC TEMP SENSOR DIGITAL SO-8
• Manufacturer: STMicroelectronics

Specifications of STCN75M2E

• Featured Product: STM32 Cortex-M3 Companion Products
• Function: Temp Sensor, Watchdog
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Full Temp Accuracy: +/- 3 C
• Digital Output - Bus Interface: Serial (2-Wire, I2C)
• Digital Output - Number Of Bits: 9 bit
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 0.5°C
• Temperature Sensing Range: -55°C To +125°C
• Supply Current: 125µA
• Supply Voltage Range: 2.7V To 5.5V
• Sensor Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional description
3.4.4
3.4.5
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Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
Figure 5.
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse (see
obliged to generate an acknowledge after the reception of each byte that has been clocked
out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
CLOCK
DATA
CONDITION
Serial bus data transfer sequence
START
Figure 6 on page
Doc ID 13307 Rev 8
DATA VALID
DATA LINE
STABLE
DATA ALLOWED
CHANGE OF
21). A slave receiver which is addressed is
CONDITION
STOP
STCN75
AI00587