MC10XS3535PNA Freescale Semiconductor, MC10XS3535PNA Datasheet - Page 3

• Manufacturer Part Number: MC10XS3535PNA
• Description: IC SWITCH HIGHSIDE 24PQFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC10XS3535PNA

• Number Of Outputs: 5
• Rds (on): 10 mOhm, 35 mOhm
• Internal Switch(s): No
• Voltage - Input: 7 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-PQFN, 24-PowerQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current Limit: -

Table 1. 10XS3535 Pin Definitions
Analog Integrated Circuit Device Data
Freescale Semiconductor
Number
A functional description of each pin can be found in the Functional Pin Description section beginning on
Pin
1
2
3
4
5
6
7
8
9
FLASHER
Pin Name
CLOCK
FETIN
SCLK
LIMP
FOG
RST
IGN
CS
Pin Function
Figure 3. 10XS3535 Pin Connections (Transparent Top View Of Package)
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input
OUT5
GND
CP
External FET Input This pin is the current sense recopy of the external SMART MOSFET.
FOG Input (Active
Limp Home Input
13
SPI Clock Input
Formal Name
Flasher Input
16
17
18
Ignition Input
(Active High)
(Active High)
(Active High)
(Active Low)
Chip Select
Clock Input
12
OUT4
Reset
high)
19
11
PIN CONNECTIONS
10
9
This input wakes the device. It also controls the Outputs 1 and 2 in case of Fail
mode activation. This pin has a passive internal pull-down.
This input wakes the device. It is also used to initialize the device configuration
and fault registers through SPI. This digital pin has a passive internal pull-down.
This input wakes the device. This pin has a passive internal pull-down.
This pin state depends on RST logic level.
As long as RST input pin is set to logic [0], this pin is pulled up in order to report
wake event. Otherwise, the PWM frequency and timing are generated from this
digital clock input by the PWM module.
This pin has a passive internal pull-down.
The Fail mode can be activated by this digital input. This pin has a passive
internal pull-down.
This input wakes the device. This pin has a passive internal pull-down.
When this digital signal is high, SPI signals are ignored. Asserting this pin low
starts a SPI transaction. The transaction is signaled as completed when this
signal returns high. This pin has a passive internal pull-up resistance.
This digital input pin is connected to the master microcontroller providing the
required bit shift clock for SPI communication. This pin has a passive internal
pull-down resistance.
8
VBAT
GND
OUT3
14
15
20
7
6
5
4
3
OUT2
21
2
24
23
22
1
Definition
CSNS
GND
OUT1
Page
PIN CONNECTIONS
20.
10XS3535
3