MC10XS3535PNA Freescale Semiconductor, MC10XS3535PNA Datasheet - Page 28

• Manufacturer Part Number: MC10XS3535PNA
• Description: IC SWITCH HIGHSIDE 24PQFN
• Manufacturer: Freescale Semiconductor
• Type: High Side Switchr

Specifications of MC10XS3535PNA

• Number Of Outputs: 5
• Rds (on): 10 mOhm, 35 mOhm
• Internal Switch(s): No
• Voltage - Input: 7 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-PQFN, 24-PowerQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current Limit: -

with bit D7 at logic [0]. This register allows the master to
control the duty cycle and the switching phases of OUT1. The
duty cycle resolution is given by bits D6 : D0.
period.
ADDRESS 01010 — CONTROL OUT2
ADDRESS 01011 — CONTROL OUT3
ADDRESS 01100 — CONTROL OUT4
ADDRESS 01101 — CONTROL OUT5
ADDRESS 01110 — CONTROL EXTERNAL SWITCH
ADDRESS 01111 — TEST MODE
SPI during normal operation.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN
DATA)
loaded. Meanwhile, the data is clocked out MSB first as the
28
10XS353
Overload
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Status /
Status
Status
Mode
Fault
Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF
D7 = 0, D6 : D0 = XX output OFF.
D7 = 1, D6 : D0 = 00 output ON during 1/128.
D7 = 1, D6 : D0 = 1A output ON during 27/128 on PWM
D7 = 1, D6 : D0 = 7F output continuous ON (no PWM).
Same description as OUT1.
Same description as OUT1.
Same description as OUT1.
Same description as OUT1.
Same description as OUT1.
This register is reserved for test and is not available with
When the
Previous
SO
A1
SI Data
0
0
CS
SO
A0
0
1
Table 9. Switching Phases
pin is pulled low, the output register is
10
11
OD15 OD14 OD13 OD12 OD11 OD10 OD9
0
0
0
1
UVF
UVF
OTW
OTW
180°
270°
OTS
OTS
Table 10. Serial Output Bit Map Description
NM
NM
OC5 OTS5 OC4 OTS4 OC3 OTS3 OC2
OL5
OVL5
OD8
new message data is clocked into the SI pin. The first 16 bits
of data clocking out of the SO, and following a
is dependant upon the previously written SPI word (SOA1
and SOA0 defined in the last SPI initialization word).
representative of the initial message bits clocked into the SI
pin since the
feature is useful for daisy chaining devices.
transition of logic [0] to logic [1]. If the message length is
valid, the data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
the Initialization-selected register data at the time that the
is pulled to a logic [0] during SPI communication and / or for
the period of time since the last valid SPI communication,
with the following exceptions:
SERIAL OUTPUT BIT ASSIGNMENT
from the most recent initialization command SOA[1:0] (refer
to
follow.
the fault is removed.
reflects Normal mode (NM).
SO Data
Table
Any bits clocked out of the SO pin after the first 16 will be
A valid message length is determined following a
The output status register correctly reflects the status of
•The previous SPI communication was determined to be
•Battery transients below 6.0 V, resulting in an under-
The contents of bits OD15 : OD0 depend on bits D1: D0
The register bits are reset by a read operation and also if
Table 10
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
voltage shutdown of the outputs, may result in incorrect
data loaded into the SPI register, except the UVF fault
reporting (OD13).
OD7
OL4
7, page 26), as explained in the paragraphs that
OVL4 OL3 OVL3
summarizes the SO register content. Bit OD10
OD6
CS
pin first transitioned to a logic [0]. This
OD5 OD4
Analog Integrated Circuit Device Data
OD3
OL2
Freescale Semiconductor
OVL2
OTS2
OD2
CS
OD1
OC1 OTS1
OL1 OVL1
transition,
CS
OD0
CS