NAND512W3A2SN6E NUMONYX, NAND512W3A2SN6E Datasheet
NAND512W3A2SN6E
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NAND512W3A2SN6E Summary of contents
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... OTP area – Serial number (unique ID) July 2010 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Numonyx® NAND SLC small page – Hardware program/erase locked during Electronic signature – Manufacturer ID: – Device ID: Package – ...
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... Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7.1 6.7.2 6.7.3 6.7.4 6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/51 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write protection bit (SR7 P/E/R controller bit (SR6 Error bit (SR0 SR5, SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . 26 210403 - Rev 2 Numonyx SLC ...
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... Numonyx SLC Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.1 7.6.2 8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 32 9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 22. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 23. TSOP48 - 48 lead plastic thin small outline mm, mechanical data . . . . . . . . . . . . 47 Table 24. VFBGA63 1. +15 active ball array, 0.8 mm pitch, mechanical data 48 Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4/51 210403 - Rev 2 Numonyx SLC ...
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... Numonyx SLC List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. VFBGA63 connections - x8 devices (top view through package Figure 5. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Pointer operations Figure 7. Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Read (A,B,C) operations Figure 9. Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10 ...
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... Serial number (unique identifier), which enables each device to be uniquely identified subject to an NDA and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. For information on how to order these devices refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’ ...
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... Numonyx SLC Table 2. Product description Root part Bus Page Density number width size 512+16 NAND512W3A2S x8 Bytes 256+8 NAND512W4A2S x16 Words 512 Mbit 512+16 NAND512R3A2S x8 Bytes 256+8 NAND512R4A2S x16 Words Figure 1. Logic diagram Block Memory Operating size array voltage 16K+512 Bytes 2.7 to 3.6 V ...
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... Command register 8/51 Function memory array P/E/R controller, high voltage generator Page buffer Y decoder I/O buffers & latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 210403 - Rev 2 Numonyx SLC Direction I/O I/O Input Input Input Input Output Input Input Power supply Ground – – ...
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... Numonyx SLC Figure 3. TSOP48 connections - x8 devices NAND Flash (x8 210403 - Rev 2 Description I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI07585C 9/51 ...
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... Description Figure 4. VFBGA63 connections - x8 devices (top view through package 10 I/O2 I/O3 I/O4 210403 - Rev 2 Numonyx SLC I/O5 I/O7 I/ AI07586B ...
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... Numonyx SLC Memory array organization The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification ...
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... Bytes Page buffer, 512 Bytes 512 Bytes 12/51 Block Page 8 bits 16 Bytes 16 8 bits Bytes 210403 - Rev 2 Numonyx SLC x16 DEVICES Block = 32 pages Page = 264 Words (256+8) Main area 16 bits 256 Words 8 Words Page buffer, 264 Words 8 16 bits 256 Words ...
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... Numonyx SLC Signal descriptions See Figure 1: Logic connected to the devices. Table 5. Signal descriptions Symbol Input/Output signals I/O0-I/O7 I/O8-I/O15 Control signals diagram, and Table 3: Signal Table 5 provides the detailed descriptions of the signals. Type Input/outputs are used to input the selected address, output the data during a read operation or input a command or data during a write operation ...
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... An internal voltage detector disables all functions whenever V Data protection) to protect the device from any involuntary program/erase operations during power-transitions. Ground, V SS, Ground be connected to the system ground. 210403 - Rev 2 Numonyx SLC Description after the falling RLQV , the device does not accept read, program or erase Section 10 ...
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... Numonyx SLC Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see 4.1 Command input Command input bus operations are used to give commands to the memory. Command are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High ...
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... Section 6.1: Pointer (1)(2) I/O7 I/O6 I/O5 I/ A16 A15 A14 A13 A24 A23 A22 A21 210403 - Rev 2 Numonyx SLC I/O0 - I/O7 I/O8 - I/O15 (2) X Command X Address X Data input Data input X Data output Data output I/O3 I/O2 I/ A12 A11 A10 A20 A19 ...
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... Numonyx SLC Table 9. Address definition Address A25 A9 - A13 A14 - A25 A8 is set Low or High by the 00h or 01h command, A8 210403 - Rev 2 Bus operations Definition Column address Page address Address in block Block address and is don’t care in x16 devices 17/51 ...
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... D0h FFh – 210403 - Rev 2 Numonyx SLC Command accepted during rd cycle busy – – – – – Yes – (4) – – Yes ...
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... Numonyx SLC Device operations 6.1 Pointer operations As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see act as pointers to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device ...
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... Data Input 10h 01h AREA C Data Input 10h 50h operations. Once the area (main or spare) has been selected using the Table 8) of the data to be read. 210403 - Rev 2 Numonyx SLC Address 80h Data Input Inputs Address 80h Data Input Inputs Address 80h ...
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... Numonyx SLC 6.2.2 Page read After the random read access the page data is transferred to the page buffer in a time of t (refer to Table 22 WHBH goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. ...
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... Block Nth page Area B Area C (spare) A9-A26 (1) A0-A7 Area B Area C (spare) A9-A26 (1) A0- A0-A2 (x 16) 210403 - Rev 2 Numonyx SLC tBLBH1 Busy 2nd Nth page output page output Area A Area C (main area) (Spare) 1st page 2nd page Nth page Area A ...
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... Numonyx SLC 6.3 Page program The page program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of Bytes (1 to 528) or Words (1 to 264) can be programmed. ...
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... Same address for source and target pages tBLBH2 (Program Busy time) Target 8Ah 10h Address Inputs Copy Back Code 210403 - Rev 2 Numonyx SLC A25 Busy (1) 70h SR0 Read Status Register ai13187 ...
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... Numonyx SLC 6.5 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists of three steps (refer to 1. One bus cycle is required to setup the Block Erase command 2 ...
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... Write protection '0' '1' '0' Reserved Don’t care ‘1’ Generic error ‘0’ 210403 - Rev 2 Numonyx SLC bits. Refer to Table 12 in Definition Not protected Protected P/E/R C inactive, device ready P/E/R C active, device busy Error – operation failed No error – operation successful ...
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... Numonyx SLC 6.8 Read electronic signature The device contains a manufacturer code and device code. To read these codes two steps are required: 1. first use one bus write cycle to issue the Read Electronic Signature command (90h), followed by an address input of 00h 2. then perform two bus read operations – the first reads the manufacturer code and the second, the device code ...
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... To help integrate a NAND memory into an application Numonyx can provide a full range of software solutions: file system, sector management, drivers, and code management. Contact the nearest Numonyx sales office or visit www.numonyx.com for more details. ...
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... Numonyx SLC Refer to Table 14 Table 14. NAND Flash failure modes Operation Erase Program Read Figure 15. Bad block management flowchart for the procedure to follow if an error occurs during an operation. START Block Address = Block 0 Data NO Bad Block table = FFh? YES Last NO block? YES END ...
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... Users must implement an error correction code (ECC) to identify and correct errors in the data stored in the NAND Flash memories. The ECC implemented must be able to correct 1 bit every 512 Bytes. Sensible data stored in the spare area must be covered by ECC as well. 30/51 Old area New area (after GC) Free page (erased) 210403 - Rev 2 Numonyx SLC AI07599B ...
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... Numonyx SLC 7.6 Hardware simulation models 7.6.1 Behavioral simulation models Denali software corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware ...
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... for less than 20 ns during transitions on I/O pins. DD 32/51 Min 100,000 10 Table 16: Absolute maximum Parameter 1.8 V devices 3 V devices 1.8 V devices 3 V devices 210403 - Rev 2 Numonyx SLC NAND Flash Unit Typ Max 200 500 µ cycles years ratings, may ...
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... Numonyx SLC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 17: Operating and AC measurement operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... Erase – E=V -0.2, WP=0V/V DD E=V -0.2, WP=0 max max OUT DD – – = −100 µ 100 µ 0 – 210403 - Rev 2 Numonyx SLC ref 2R ref Ai11085 Min Typ Max – – – – – – – – ±10 – – ±10 V -0.4 – ...
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... Numonyx SLC Table 20. DC characteristics devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (TTL) DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input high voltage IH V Input low voltage IL V Output high voltage level ...
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... Read Enable High hold time Read Enable pulse width Read cycle time Read Enable access time (1) Read ES access time Read busy time is the delay from WP High to W High. During a program/erase disable VHWH 210403 - Rev 2 Numonyx SLC 1 Unit devices devices Min Min ...
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... Numonyx SLC Figure 18. Command Latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 19. Address Latch AC waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH (AL Setup time) tWHALL (AL Hold time) AL tDVWH (Data Setup time) I/O tWLWH tDVWH (Data Setup time) ...
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... Figure 21. Sequential data output after read AC waveforms Low Low High. 38/51 tWLWL tWLWH tDVWH tDVWH tWHDX (Data Hold time) Data In 0 Data In 1 210403 - Rev 2 Numonyx SLC tWHCLH (CL Hold time) tWHEH (E Hold time) tWLWH tDVWH tWHDX tWHDX Data In Last tEHQX tEHQZ ...
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... Numonyx SLC Figure 22. Read status register AC waveforms tCLHWH tELWH Figure 23. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. Refer to Table 13 for the values of the manufacturer and device codes. tALLRL1 tRLQV (Read ES Access time) Man. Device 00h code code 1st Cycle ...
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... Data Add.N Add.N Add.N cycle 2 cycle 3 cycle 4 Address N Input Busy from Address N to Last Byte or Word in Page 210403 - Rev 2 Numonyx SLC tEHQZ tRLRL tRHQZ (Read Cycle time) Data Data Data N N+1 N+2 Last Data Output tRHQX tEHQX ...
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... Numonyx SLC Figure 25. Read C operation, one page AC waveforms Add. M I/O 50h cycle 1 RB Command Code 1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are don’t care. tWHALL Add. M Add. M Add. M cycle 2 cycle 3 cycle 4 Address M Input ...
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... RB Page Program Setup Code 42/51 tWLWL tWHBL Add.N Add.N Add.N N cycle 4 cycle 2 cycle 3 Address Input Data Input 210403 - Rev 2 Numonyx SLC tWLWL tBLBH2 (Program Busy time) Last 10h 70h Confirm Page Code Program Read Status Register SR0 ai08037 ...
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... Numonyx SLC Figure 27. Block erase AC waveforms CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 28. Reset AC waveforms I/O FFh RB tBLBH3 tWHBL (Erase Busy time) Add. Add. D0h cycle 2 cycle 3 Confirm Block Erase ...
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... Figure 33 show the electrical characteristics for the Ready/Busy can be calculated using the following equation – V DDmax V OLmax R P min = ------------------------------------------------------------- + I OL 1.85V ( ) R P min 1.8V = --------------------------- 3mA 3. min 3V = --------------------------- 8mA . r 210403 - Rev 2 Numonyx SLC 10h 10h ) ai12477 ai12478 P ...
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... Numonyx SLC Figure 31. Ready/Busy AC waveform Figure 32. Ready/Busy load circuit 1.8 V device - 0 0.1 V 3.3 V device - 0 2.4 V ready busy DEVICE RB Open Drain Output V SS 210403 - Rev 2 DC and AC parameters NI3087 ibusy AI07563B 45/51 ...
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... DC and AC parameters Figure 33. Resistor value versus waveform timings for Ready/Busy signal 25°C. 10.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD Low ( guarantee hardware protection during power transitions as shown in the figure ...
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... Numonyx SLC Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... FE1 millimeters Min Max 1.05 0.25 0.40 0.50 8.90 9.10 0.10 10.90 11.10 0.80 0.40 0.40 210403 - Rev 2 Numonyx SLC ddd A2 BGA-Z75 inches Typ Min 0.010 0.026 0.018 0.016 0.354 0.350 0.157 0.283 0.433 0.429 0.220 0.346 0.031 0.098 0.035 0.106 ...
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... Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape & reel packing Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. NAND512W3A 2 210403 - Rev 2 ...
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... Revision history 13 Revision history Table 26. Document revision history Date 03-Feb-2010 29-Jul-2010 50/51 Revision 1 Initial release. 2 Added information about 1.8 V devices. 210403 - Rev 2 Numonyx SLC Changes ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...