PCA9601DP,118 NXP Semiconductors, PCA9601DP,118 Datasheet
PCA9601DP,118
Specifications of PCA9601DP,118
Available stocks
Related parts for PCA9601DP,118
PCA9601DP,118 Summary of contents
Page 1
PCA9601 Dual bidirectional bus buffer Rev. 01 — 28 May 2010 1. General description The PCA9601 is designed to isolate I driven in point-to-point or multipoint applications 4000 pF. The PCA9601 is a higher-speed version of the ...
Page 2
... NXP Semiconductors 3. Applications Interface between Interface between I Simple conversion of I hardware, for example, via compatible PCA82C250 Interfaces with opto-couplers to provide opto-isolation between I 1 MHz Long distance point-to-point or multipoint architectures 4. Ordering information Table 1. Type number PCA9601D PCA9601DP 4.1 Ordering options Table 2. Type number ...
Page 3
... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. Symbol GND PCA9601_1 Product data sheet PCA9601D GND TY 002aae874 Pin configuration for SO8 Pin description Pin Description C-bus (SDA or SCL) 2 receive signal 3 transmit signal 4 negative supply voltage 5 transmit signal 6 receive signal ...
Page 4
... NXP Semiconductors 7. Functional description Refer to The PCA9601 has two identical buffers allowing buffering of SDA and SCL I signals. Each buffer is made up of two logic signal paths, a forward path from the I interface, pins SX and SY which drive the buffered bus, and a reverse signal path from the buffered bus input, pins RX and RY to drive the I • ...
Page 5
... NXP Semiconductors 7.2 High drive, long distance side The logic level determined from the power supply voltage V LOW is below threshold just slightly below half open-collector output without ESD protection diodes to V via a pull-up resistor to a supply voltage in excess of V exceeded. It has a larger current sinking capability than a normal I able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well ...
Page 6
... NXP Semiconductors 7.4 Comparison of PCA9601/PCA9600 and P82B96 The PCA9601 is a direct upgrade of the P82B96 with the significant differences summarized in Fast-mode Plus devices on the SX/SY sides. Table 4. PCA9601/PCA9600 versus P82B96 Detail Supply voltage (V ) range: CC Maximum operating bus voltage (independent Typical operating supply current: ...
Page 7
... NXP Semiconductors • When the operating temperature range is restricted at both limits typical output is well below 0.4 V and the P82B96 typically requires 0.6 V input even at +60 °C, so there is a reasonable margin. The PCA9601/PCA9600 requires a typical input low of 0 its typical margin is smaller °C the driver requires a typical input low of 1 ...
Page 8
... NXP Semiconductors 9. Characteristics Table 6. Characteristics − ° ° +85 C unless otherwise specified; voltages are specified with respect to GND with V amb unless otherwise specified. Typical values are measured at V Symbol Parameter Power supply V supply voltage CC I supply current CC ΔI additional supply current ...
Page 9
... NXP Semiconductors Table 6. Characteristics …continued − ° ° +85 C unless otherwise specified; voltages are specified with respect to GND with V amb unless otherwise specified. Typical values are measured at V Symbol Parameter Output logic LOW level Pins SX and SY V LOW-level output voltage OL ΔV/ΔT ...
Page 10
... NXP Semiconductors Table 6. Characteristics …continued − ° ° +85 C unless otherwise specified; voltages are specified with respect to GND with V amb unless otherwise specified. Typical values are measured at V Symbol Parameter [5] Buffer response time = 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.2 kΩ; no capacitive load ...
Page 11
... NXP Semiconductors Fig 4. 800 V OL (mV) 700 (1) (2) 600 500 400 −50 − typical and limits over temperature. OL (1) Maximum. (2) Typical. Fig function of junction temperature 0.3 mA) OL 600 V IL (mV) 500 400 300 200 −50 − changes over temperature range. IL Fig function of junction temperature; ...
Page 12
... NXP Semiconductors 1400 V CC(max) (mV) 1200 1000 800 600 400 −50 − Fig 9. V bus release limit over temperature; CC maximum values Fig 11. Typical SX/SY current versus LOW-level output voltage PCA9601_1 Product data sheet 002aac075 I (μA) 75 100 125 T (°C) j Fig 10. Current sourced out of SX/ function of 1 ...
Page 13
... NXP Semiconductors 10. Application information Refer to application notes AN10658 and AN255 for more detailed application information. Fig 12. Interfacing a standard Fig 13. Galvanic isolation of I SDA SCL Fig 14. Long distance I PCA9601_1 Product data sheet C-bus SDA PCA9601 2 C-bus or one with TTL levels (e.g. SMBus) to higher voltage or higher current sink (e ...
Page 14
... NXP Semiconductors V CC1 R2 R2 SCL C-BUS MASTER SDA SY PCA9601 C2 C2 GND Fig 15. Driving ribbon or flat telephone cables Table 7. Examples of bus capability Refer to Figure 15 CC1 CC2 (V) cable (V) (Ω) (kΩ) ( 750 2 750 2.2 3.3 5 3.3 330 1 3.3 5 3.3 330 1 For more examples of faster alternatives for driving over longer cables such as Cat5 communication cable, see AN10658. Communication at 1 MHz is possible over short cables and > ...
Page 15
... NXP Semiconductors 10.1 Calculating system delays and bus clock frequency local master bus V CCM SCL MASTER 2 I C-BUS GND (0 V) Effective delay of SCL at slave: 120 + 17V Fig 16. Falling edge of SCL at master is delayed by the buffers and bus fall times V CCM MASTER 2 I C-BUS Effective delay of SCL at master: 115 + (Rm × ...
Page 16
... NXP Semiconductors local master bus V CCM SDA MASTER 2 I C-BUS GND (0 V) Effective delay of SDA at master: 115 + 0.2(Rs × Cs) + 0.7[(Rb × Cb) + (Rm × Cm)] (ns Ω. Fig 18. Rising edge of SDA at slave is delayed by the buffers and bus rise times Figure 16, with relatively large capacitances linking two I expressions for making the relevant timing calculations for 3 ...
Page 17
... NXP Semiconductors from the master reaching the slave SCL rising edge SDA, reaching the master The master microcontroller should be programmed to produce a nominal SCL LOW period as follows: SCL LOW The actual LOW period will become (the programmed value + the stretching time B). ...
Page 18
... NXP Semiconductors The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+ 500 ns requirement. This system requires the bus LOW period, and therefore cycle time increased the system must run slightly below the 1 MHz limit. The possible maximum speed has a cycle period of 1033 ns or 968 kHz. ...
Page 19
... NXP Semiconductors ( −1 0 100 200 300 400 500 600 700 800 (1) TX output. (2) SX input. Fig 20. Propagation with V (SX pull- pull-up to 5.7 V) (1) RX input. (2) SX output. Fig 22. Propagation (SX pull- 10.2 Negative undershoot below absolute minimum value The reason why the IC pin reverse voltage on pins TX and specified at such a low value, − ...
Page 20
... NXP Semiconductors testing but it was not damaged. Whenever there is current flowing in any of these diodes it is possible that there can be faulty operation of any IC. For that reason we put a specification on the negative voltage that is allowed to be applied selected so that, at the highest allowed junction temperature, there will be a big safety factor that guarantees the diode will not conduct and then we do not need to make any 100 % production tests to guarantee the published specification ...
Page 21
... NXP Semiconductors 10.2.1 Example with questions and answers Question falling edge measure undershoot at −800 mV at the linked TX, RX pins of the PCA9601 that is generating the LOW, but the PCA9601 data sheet specifies minimum −0.3 V. Does this mean that we violate the data sheet absolute value? Answer: For PCA9601 the − ...
Page 22
... NXP Semiconductors Question: We have 2 meters of cable in a bus that joins the TX/RX sides of two PCA9601 devices. When one TX drives LOW the other PCA9601 TX/RX is driven to −0.8 V for over 50 ns. What is the expected value and the theoretically allowed value of undershoot? Answer: Because the cable joining the two PCA9601s is a ‘transmission line’ that will have a characteristic impedance around 100 Ω ...
Page 23
... NXP Semiconductors Question add 100 Ω to 200 Ω at signal line, the overshoot becomes slightly smaller. Is this a good idea? Answer: No not necessary to add any resistance. When the logic signal generated PCA9601 drives long traces or wiring with ICs other than PCA9601 being driven, then adding a Schottky diode (BAT54A) as shown in the wiring undershoot to a value that will not cause conduction of the IC’ ...
Page 24
... NXP Semiconductors 11. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 25
... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 26
... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 27
... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 28
... NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 10. Acronym CDM ESD HBM 2 I C-bus I PMBus SCL SDA SMBus TTL 14. Revision history Table 11. ...
Page 29
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 30
... For sales office addresses, please send an email to: PCA9601_1 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 31
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Static level offset card side . . . . . . . . . . . . . . . . 4 7.1.1 Fast-mode operation . . . . . . . . . . . . . . . . . . . . 4 7.1.2 Fast-mode Plus operation ...