PIC18F26K80-I/SP Microchip Technology, PIC18F26K80-I/SP Datasheet - Page 501
![MCU PIC 64KB FLASH 28SDIP](/photos/18/99/189989/4243185_sml.jpg)
PIC18F26K80-I/SP
Manufacturer Part Number
PIC18F26K80-I/SP
Description
MCU PIC 64KB FLASH 28SDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F26K80-I/SP
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18F26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F26K80-I/SP
Manufacturer:
MICROCHIP
Quantity:
2 000
- Current page: 501 of 628
- Download datasheet (6Mb)
BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2011 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction:
After Instruction:
Decode
PORTC =
PORTC =
Q1
register ‘f’
BTG
Bit Toggle f
BTG f, b {,a}
0 f 255
0 b < 7
a [0,1]
(f<b>) f<b>
None
Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
Read
0111
Q2
0111 0101 [75h]
0110 0101 [65h]
PORTC,
bbba
Process
Data
Q3
4, 0
for details.
ffff
register ‘f’
Write
Q4
ffff
Preliminary
PIC18F66K80 FAMILY
BOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Overflow
If Overflow
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Overflow
BOV
-128 n 127
if Overflow bit is ‘ 1 ’,
(PC) + 2 + 2n PC
None
If the Overflow bit is ‘ 1 ’, then the
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
1 ;
address (Jump)
0 ;
address (HERE + 2)
0100
BOV
operation
Process
Process
Data
Data
No
Q3
Q3
DS39977C-page 501
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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