MSC8144VT800A Freescale Semiconductor, MSC8144VT800A Datasheet - Page 2

• Manufacturer Part Number: MSC8144VT800A
• Description: IC DSP QUAD 800MHZ 783FCBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC3400 Corer

Specifications of MSC8144VT800A

• Interface: Ethernet, I²C, SPI, TDM, UART, UTOPIA
• Clock Rate: 800MHz
• Non-volatile Memory: External
• On-chip Ram: 10.5MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.00V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2
3
4
5
6
7
List of Figures
Figure 1. MSC8144 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram 3
Figure 3. MSC8144 FC-PBGA Package, Top View . . . . . . . . . . . . 4
Figure 4. MSC8144 FC-PBGA Package, Bottom View . . . . . . . . . 5
Figure 5. SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31
Figure 6. Start-Up Sequence with V
Figure 7. Timing for a Reset Configuration Write . . . . . . . . . . . . . 38
Figure 8. Timing for t
Figure 9. DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41
Figure 10.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11.Differential V
2
Pin Assignments and Reset States. . . . . . . . . . . . . . . . . . . . . .4
1.1
1.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.1
2.2
2.3
2.4
2.5
2.6
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .64
3.1
3.2
3.3
3.4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Recommended Operating Conditions. . . . . . . . . . . . . .27
Default Output Driver Characteristics . . . . . . . . . . . . . .28
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29
AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Start-up Sequencing Recommendations . . . . . . . . . . .64
Power Supply Design Considerations. . . . . . . . . . . . . .66
Clock and Timing Signal Board Layout Considerations 67
Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .67
CLKIN Started with V
DDKHMH
PP
of Transmitter or Receiver . . . . . . . . . . 42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DDIO
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
DD
. . . . . . . . . . . . . . . . . . . . . . . 35
Raised Before V
Table of Contents
DDIO
with
Figure 12.Transmitter Output Compliance Mask . . . . . . . . . . . . . . 46
Figure 13.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 48
Figure 14.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 49
Figure 15.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16.PCI Input AC Timing Measurement Conditions . . . . . . . 51
Figure 17.PCI Output AC Timing Measurement Condition . . . . . . 51
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 21.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 22.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 23.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . . 55
Figure 25.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 27.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 28.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . 57
Figure 29.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 30.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 31.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 59
Figure 32.ATM/UTOPIA/POS AC Test Load . . . . . . . . . . . . . . . . . 60
Figure 33.ATM/UTOPIAPOS AC Timing (External Clock) . . . . . . . 60
Figure 34.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 35.SPI AC Timing in Slave Mode (External Clock). . . . . . . 61
Figure 36.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 62
Figure 37.Asynchronous Signal Timing . . . . . . . . . . . . . . . . . . . . . 62
Figure 38.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 39.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 63
Figure 40.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 41.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 42.V
Figure 44.MSC8144 Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DDM3
, V
DDM3IO
and V
25M3
Power-on Sequence . . . . . 65
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