MAX7032ATJ+ Maxim Integrated Products, MAX7032ATJ+ Datasheet - Page 21

• Manufacturer Part Number: MAX7032ATJ+
• Description: RF Transceiver IC TXRX ASK/FSK PROG MHz Crystal-Based, P
• Manufacturer: Maxim Integrated Products

Specifications of MAX7032ATJ+

• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 300 MHz to 450 MHz
• Output Power: 6.7 dBm
• Operating Supply Voltage: 2.7 V, 5 V
• Maximum Operating Temperature: + 125C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 12.5 mA
• Minimum Operating Temperature: - 40 C
• Modulation: ASK/OOK.FSK
• Package / Case: TQFN-32 EP
• Data Rate: 33Kbps
• Supply Voltage Range: 2.1V To 3.6V, 4.5V To 5.5V
• Logic Case Style: QFN
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +125°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 66Kbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In continuous receive mode, individual analog modules
can be powered on directly through the power configu-
ration register (register 0x00). The SLEEP bit (bit 0 in
register 0x01) overrides the power configuration regis-
ters and puts the device into deep-sleep mode when
set. It is also necessary to write the frequency divisor of
the external crystal in the oscillator frequency register
(register 0x05) to optimize image rejection and to
enable accurate calibration sequences for the polling
timer and the FSK demodulator. This number is the
integer result of f
If the FSK receive function is selected, it is necessary to
perform an FSK calibration to allow operation; other-
wise, the demodulator is saturated. Polling timer cali-
bration is not necessary. See the Calibration section for
more information.
In the discontinuous receive mode (DRX = 1), the
receiver modules set to logic 1 by the power register
(0x00) of the MAX7032 toggle between OFF and ON,
according to internal timers t
Table 4. Register Configuration
POWER[7:0] (0x00)
CONTRL[7:0] (0x01)
CONF0[7:0] (0x02)
CONF1[7:0] (0x03)
OSC[7:0] (0x05)
t
t
t
t
t
t
t
TxLOW[15:8] (0x0D)
TxLOW[7:0] (0x0E)
TxHIGH[15:8] (0x0F)
TxHIGH[7:0] (0x10)
STATUS[7:0] (0x1A)
OFF
OFF
CPU
RF
RF
ON
ON
NAME (ADDRESS)
[15:8] (0x09)
[7:0] (0x0A)
[15:8] (0x0B)
[7:0] (0x0C)
[15:8] (0x06)
[7:0] (0x07)
[7:0] (0x08)
ASK/FSK Transceiver with Fractional-N PLL
Discontinuous Receive Mode (DRX = 1)
Low-Cost, Crystal-Based, Programmable,
XTAL
Continuous Receive Mode (DRX = 0)
______________________________________________________________________________________
/100kHz.
LNA
AGCLK
MODE
X
OSC7
t
t
t
t
t
t
t
TxL15
TxL7
TxH15
TxH7
LCKD
OFF
OFF
CPU
RF
RF
ON
ON
15
7
15
7
D7
15
7
7
OFF
, t
CPU
AGC
GAIN
ACAL
OSC6
t
t
t
t
t
t
t
TxL14
TxL6
TxH14
TxH6
GAINS
T/R
OFF
OFF
CPU
RF
RF
ON
ON
14
6
, t
14
6
D6
14
6
6
RF
, and t
TRK_EN
CLKOF
OSC5
TxH13
TxH5
CLKON
MIXER
MGAIN
t
t
t
t
t
t
t
TxL13
TxL5
OFF
OFF
CPU
RF
RF
ON
ON
ON
13
5
13
5
D5
13
5
5
. It
BaseB
X
DRX
CDIV1
OSC4
t
t
t
t
t
t
t
TxL12
TxL4
TxH12
TxH4
0
OFF
OFF
CPU
RF
RF
ON
ON
is also necessary to write the frequency divisor of the
external crystal in the oscillator frequency register (reg-
ister 0x05). This number is the integer result of
f
receive mode for the first time, it is also necessary to
calibrate the timers (see the Calibration section).
The MAX7032 uses a series of internal timers (t
t
The timer sequence begins when both CS and DIO are
one. The MAX7032 has an internal pullup on the DIO
pin, so the user must tri-state the DIO line when CS
goes high.
The external CPU can then go to a sleep mode during
t
DIO serves as the wake-up signal for the CPU, which
must then start its wake-up procedure and drive DIO
low before t
expires and t
data output. The CPU must then keep DIO low for as
long as it may need to analyze any received data.
Releasing DIO after t
to pull up DIO, reinitiating the t
CPU
OFF
XTAL
12
4
12
4
D4
12
4
4
. A high-to-low transition on DIO or a low level on
, t
/100kHz. Before entering the discontinuous
DATA
RF
, and t
PkDet
PCAL
OFPS1
CDIV0
OSC3
t
t
t
t
t
t
t
TxL11
TxL3
TxH11
TxH3
0
OFF
OFF
CPU
RF
RF
ON
ON
LOW
11
3
11
3
D3
ON
11
3
3
ON
expires (t
is active, the MAX7032 enables the
) to control its power-up sequence.
ON
PA
FCAL
OFPS0
DT2
OSC2
t
t
t
t
t
t
t
TxL10
TxL2
TxH10
TxH2
0
OFF
OFF
CPU
RF
RF
ON
ON
10
2
10
2
D2
expires causes the MAX7032
10
2
2
CPU
OFF
+ t
RSSIO
CKOUT
ONPS1
DT1
OSC1
t
t
t
t
t
t
t
TxL9
TxL1
TxH9
TxH1
PCALD
OFF
OFF
CPU
RF
RF
ON
ON
timer.
RF
9
1
9
1
D1
9
1
1
+ t
ON
). Once t
X
SLEEP
ONPS0
DT0
OSC0
t
t
t
t
t
t
t
TxL8
TxL0
TxH8
TxH0
FCALD
OFF
OFF
CPU
RF
RF
ON
ON
8
0
D0
8
0
8
0
0
OFF
21
RF
,