MAX7032ATJ+ Maxim Integrated Products, MAX7032ATJ+ Datasheet - Page 12

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MAX7032ATJ+

Manufacturer Part Number
MAX7032ATJ+
Description
RF Transceiver IC TXRX ASK/FSK PROG MHz Crystal-Based, P
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX7032ATJ+

Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
300 MHz to 450 MHz
Output Power
6.7 dBm
Operating Supply Voltage
2.7 V, 5 V
Maximum Operating Temperature
+ 125C
Mounting Style
SMD/SMT
Maximum Supply Current
12.5 mA
Minimum Operating Temperature
- 40 C
Modulation
ASK/OOK.FSK
Package / Case
TQFN-32 EP
Data Rate
33Kbps
Supply Voltage Range
2.1V To 3.6V, 4.5V To 5.5V
Logic Case Style
QFN
No. Of Pins
32
Operating Temperature Range
-40°C To +125°C
Filter Terminals
SMD
Rohs Compliant
Yes
Data Rate Max
66Kbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
12
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PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
4
5
6
7
8
9
3
LNAOUT
CLKOUT
LNASRC
MIXOUT
ENABLE
PDMAX
PAVDD
PAOUT
MIXIN+
TX/RX1
TX/RX2
PDMIN
MIXIN-
NAME
LNAIN
ROUT
AVDD
DVDD
DATA
IFIN+
IFIN-
RSSI
DS+
OP+
DS-
T/R
DF
Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close
as possible to the pin.
Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close as possible to the inductor with 680pF and 220pF capacitors as shown in the Typical
Application Circuit.
Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.
Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit.
Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which may be part of the output-matching network to an antenna.
Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation.
Bypass AVDD to GND with 0.1µF and 220pF capacitors placed as close as possible to the pin.
Low-Noise Amplifier Input. Must be AC-coupled.
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple
to MIXIN+.
Noninverting Mixer Input. Must be AC-coupled to the LNA output.
Inverting Mixer Input. Bypass to AV
330Ω Mixer Output. Connect to the input of the 10.7MHz filter.
Inverting 330Ω IF Limiter Amplifier Input. Bypass to GND with a capacitor.
Noninverting 330Ω IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.
Minimum-Level Peak Detector for Demodulator Output
Maximum-Level Peak Detector for Demodulator Output
Inverting Data Slicer Input
Noninverting Data Slicer Input
Noninverting Op Amp Input for the Sallen-Key Data Filter
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Buffered Received-Signal-Strength Indicator Output
Transmit/ Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down. This function is also controlled by a
configuration register.
Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into
shutdown mode.
Receiver Data Output/Transmitter Data Input
Divided Crystal Clock Buffered Output
Digital Power-Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close as
possible to the pin.
DD
with a capacitor as close as possible to LNA LC tank filter.
FUNCTION
Pin Description

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