MAX7032ATJ+ Maxim Integrated Products, MAX7032ATJ+ Datasheet - Page 15

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MAX7032ATJ+

Manufacturer Part Number
MAX7032ATJ+
Description
RF Transceiver IC TXRX ASK/FSK PROG MHz Crystal-Based, P
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX7032ATJ+

Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
300 MHz to 450 MHz
Output Power
6.7 dBm
Operating Supply Voltage
2.7 V, 5 V
Maximum Operating Temperature
+ 125C
Mounting Style
SMD/SMT
Maximum Supply Current
12.5 mA
Minimum Operating Temperature
- 40 C
Modulation
ASK/OOK.FSK
Package / Case
TQFN-32 EP
Data Rate
33Kbps
Supply Voltage Range
2.1V To 3.6V, 4.5V To 5.5V
Logic Case Style
QFN
No. Of Pins
32
Operating Temperature Range
-40°C To +125°C
Filter Terminals
SMD
Rohs Compliant
Yes
Data Rate Max
66Kbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 1:
where f
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
Choosing standard capacitor values changes C
470pF and C
C
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the nega-
tive input of the data-slicer comparator.
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
3 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the thresh-
old tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.
With this configuration, a long string of NRZ zeros or ones
can cause the threshold to drift. This configuration works
F1
and C
C
C
is the desired 3dB corner frequency.
F
C
F2
ASK/FSK Transceiver with Fractional-N PLL
1
F
=
F2
2
are named C16 and C17, respectively.
( .
=
1 414 100
to 220pF. In the Typical Application Circuit ,
( )(
Low-Cost, Crystal-Based, Programmable,
C
C
4 100
______________________________________________________________________________________
F
F
1
2
)(
=
=
a
k
4 100
(
(
1 000
100
1 414
k
.
)( .
.
3 14 5
)( .
k
k
3 14 5
b
a
)( )( )
)( )( )
)(
π
π
)(
kHz
f
C
f
C
kHz
)
)
225
450
Data Slicer
pF
pF
F1
to
best if a coding scheme, such as Manchester coding,
which has an equal number of zeros and ones, is used.
Figure 4 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
The maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 4, create DC output voltages equal to
the high and low peak values of the filtered ASK or FSK
demodulated signals. The resistors provide a path for
the capacitors to discharge, allowing the peak detec-
tors to dynamically follow peak changes of the data fil-
ter output voltages.
Figure 2. Sallen-Key Lowpass Data Filter
Figure 3. Generating Data Slicer Threshold Using a Lowpass
Filter
DATA
DS+
MAX7032
C
C
DATA
SLICER
F2
MAX7032
DS-
OP+
100kΩ
R
FSK DEMOD
RSSI OR
DF
DS+
100kΩ
C
F1
Peak Detectors
15

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