APA075-PQG208 Actel, APA075-PQG208 Datasheet - Page 41

• Manufacturer Part Number: APA075-PQG208
• Description: FPGA - Field Programmable Gate Array 75K System Gates
• Manufacturer: Actel

Specifications of APA075-PQG208

• Processor Series: APA075
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 27648
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 75 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operating Conditions
Table 2-17
Table 2-17 • Absolute Maximum Ratings*
Table 2-18 • Programming, Storage, and Operating Limits
Performance Retention
For devices operated and stored at 110°C or less, the
performance
programming. For devices operated and stored at
temperatures greater than 110°C, refer to
page 2-32
period. Actel does not guarantee performance if the
performance retention period is exceeded. Designers can
determine the performance retention period from the
following table.
Evaluate the percentage of time spent at the highest
temperature,
temperature to which the device will be exposed. In
Table 2-19 on page
that most closely matches the application.
Product Grade
Commercial
Industrial
Military
MIL-STD-883
Parameter
Supply Voltage Core (V
Supply Voltage I/O Ring (V
DC Input Voltage
PCI DC Input Voltage
PCI DC Input Clamp Current (absolute)
LVPECL Input Voltage
GND
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
and
to determine the performance retention
Table 2-18
retention
then
Programming Cycles (min.)
DD
2-32, find the temperature profile
)
DDP
determine
delineate operating limits.
)
period
500
500
100
100
is
the
20
V
next
IN
Table 2-19 on
years
< –1 or V
Condition
highest
Refer to
Refer to
Program Retention (min.)
after
IN
= V
Table 2-19 on page 2-32
Table 2-19 on page 2-32
v5.9
DDP
20 years
20 years
Example – the ambient temperature of a system cycles
between 100°C (25% of the time) and 50°C (75% of the
time). No forced ventilation cooling system is in use. An
APA600-PQ208M
dissipating
(junction-to-ambient) in still air
that the junction temperature of the FPGA will be 120°C
(25% of the time) and 70°C (75% of the time). The entry
in
the application, is 25% at 125°C with 75% at 110°C.
Performance retention in this example is at least 16.0
years.
Note that exceeding the stated retention period may
result in a performance degradation in the FPGA below
the worst-case performance indicated in the Actel Timer.
To ensure that performance does not degrade below the
worst-case values in the Actel Timer, the FPGA must be
reprogrammed
period. In addition, note that performance retention is
independent of whether or not the FPGA is operating.
The retention period of a device in storage at a given
temperature will be the same as the retention period of
a device operating at that junction temperature.
+ 1 V
Table 2-19 on page
Minimum
1 W.
–0.3
–0.3
–0.3
–1.0
–0.3
10
0
within
Storage Temperature
FPGA
The
–55°C
–55°C
–65°C
–65°C
Min.
2-32, which most closely matches
ProASIC
package
the
operates
Maximum
V
V
V
DDP
DDP
DDP
performance
Θ
110°C
110°C
150°C
150°C
Max.
PLUS
3.0
4.0
ja
0
+ 0.3
+ 0.5
+ 1.0
is 20°C/W, indicating
thermal
Flash Family FPGAs
in
Temperature
the
Operating
Junction
T
110°C
110°C
150°C
150°C
J
resistance
retention
Units
Max.
mA
system,
V
V
V
V
V
V
2-31