APA075-PQG208 Actel, APA075-PQG208 Datasheet - Page 21

• Manufacturer Part Number: APA075-PQG208
• Description: FPGA - Field Programmable Gate Array 75K System Gates
• Manufacturer: Actel

Specifications of APA075-PQG208

• Processor Series: APA075
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 27648
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 75 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The clock conditioning circuit can advance or delay the
clock up to 8 ns (in increments of 0.25 ns) relative to the
positive edge of the incoming reference clock. The system
also allows for the selection of output frequency clock
phases of 0° and 180°.
Prior to the application of signals to the rib drivers, they
pass through programmable delay units, one per global
network. These units permit the delaying of global
Notes:
1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments.
2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns.
3. OBDIV will also divide the phase-shift since it takes place after the PLL Core.
Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram
Clock Conditioning Circuitry Detailed Block Diagram
P-
P+
Clock from Core
Clock from Core
(GLINT mode)
(GLINT mode)
Input Pins to the PLL
CLKA
CLK
See Figure 2-15
on page 2-15
EXTFB
+
-
XDLYSEL
Global MUX B OUT
External Feedback Signal
Global MUX A OUT
0
1
FIVDIV[4:0]
FBDIV[5:0]
÷m
÷n
Deskew
Delay
2.95 ns
Bypass Secondary
Bypass Primary
PLL Core
AVDD
FBSEL[1:0]
3
1
2
Clock Conditioning
v5.9
(Top level view)
AGND
180°
FBDLY[3:0]
signals relative to other signals to assist in the control of
input set-up times. Not all possible combinations of input
and output modes can be used. The degrees of freedom
available in the bidirectional global pad system and in
the clock conditioning circuit have been restricted. This
avoids unnecessary and unwieldy design kit and software
work.
Delay Line
0.25 ns to
4.00 ns,
16 steps,
0.25 ns
increments
Circuitry
0°
V DD
3
1
2
1
7
6
5
4
2
GND
OAMUX[1:0]
OBMUX[2:0]
27
4
8
OADIV[1:0]
OBDIV[1:0]
÷v
GLA
GLB
Flash
Configuration Bits
Dynamic
Configuration Bits
÷u
ProASIC
0
Delay Line 0.0 ns, 0.25 ns,
0.50 ns and 4.00 ns
Delay Line 0.0 ns, 0.25 ns,
0.50 ns and 4.00 ns
PLUS
DLYA[1:0]
DLYB[1:0]
Flash Family FPGAs
GLB
GLA
2-11