A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 92
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A3P250-VQG100
Manufacturer Part Number
A3P250-VQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P250-VQG100
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
157
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250-VQG100
Manufacturer:
NXP
Quantity:
3 400
Part Number:
A3P250-VQG100
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P250-VQG100I
Manufacturer:
ACTEL
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100T
Manufacturer:
Microsemi SoC
Quantity:
10 000
ProASIC3 DC and Switching Characteristics
Table 2-100 • Output Enable Register Propagation Delays
2- 78
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
Description
J
= 70°C, Worst-Case VCC = 1.425 V
R e visio n 9
Table 2-6 on page 2-6
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.44 0.50 0.58
0.00 0.00 0.00
0.67 0.76 0.89
0.67 0.76 0.89
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
–2
for derating values.
–1
Std. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns