A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 10
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A3P250-VQG100
Manufacturer Part Number
A3P250-VQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P250-VQG100
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
157
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250-VQG100
Manufacturer:
NXP
Quantity:
3 400
Part Number:
A3P250-VQG100
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P250-VQG100I
Manufacturer:
ACTEL
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100T
Manufacturer:
Microsemi SoC
Quantity:
10 000
ProASIC3 Device Family Overview
Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)
1 - 4
Decryption
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch
interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT)
equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile
capability is unique to the Actel ProASIC family of third-generation architecture flash FPGAs. VersaTiles
are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout
the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is
possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming
of ProASIC3 devices via an IEEE 1532 JTAG interface.
VersaTiles
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASIC
tiles. The ProASIC3 VersaTile supports the following:
ISP AES
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
User Nonvolatile
FlashROM
Bank 0
Bank 2
R e vi s i o n 9
Charge Pumps
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
(A3P600 and A3P1000)
I/Os
CCC
VersaTile
PLUS®
core