A3P600L-FGG256 Actel, A3P600L-FGG256 Datasheet - Page 156
A3P600L-FGG256
Manufacturer Part Number
A3P600L-FGG256
Description
FPGA - Field Programmable Gate Array 6K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P600L-FGG256
Processor Series
A3P600
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
177
Data Ram Size
110592
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P600L-FGG256
Manufacturer:
ACT
Quantity:
24
Company:
Part Number:
A3P600L-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P600L-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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ProASIC3L DC and Switching Characteristics
2- 14 2
Table 2-213 • FIFO – Applies to 1.2 V DC Core Voltage
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
RCKEF
WCKFF
CKAF
RSTFG
RSTAF
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
derating values.
Worst Commercial-Case Conditions: T
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
BLK_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
Clock High to New Data Valid on DO (flow-through)
Clock High to New Data Valid on DO (pipelined)
RCLK High to Empty Flag Valid
WCLK High to Full Flag Valid
Clock High to Almost Empty/Full Flag Valid
RESET_B Low to Empty/Full Flag Valid
RESET_B Low to Almost Empty/Full Flag Valid
RESET_B Low to Data Out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle Time
Maximum Frequency for FIFO
Description
R e visio n 9
J
= 70°C, VCC = 1.14 V
Table 2-6 on page 2-7
1.84
0.02
0.40
0.00
0.24
0.00
3.14
1.19
2.29
2.18
8.25
2.26
8.17
1.23
1.23
0.38
2.00
0.63
5.75
174
–1
0.03
Std.
2.16
0.47
0.00
0.29
0.00
3.69
1.40
2.69
2.56
9.70
2.65
9.60
1.45
1.45
0.45
2.35
0.72
6.61
151
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for
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