A3P600L-FGG256 Actel, A3P600L-FGG256 Datasheet - Page 111
A3P600L-FGG256
Manufacturer Part Number
A3P600L-FGG256
Description
FPGA - Field Programmable Gate Array 6K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P600L-FGG256
Processor Series
A3P600
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
177
Data Ram Size
110592
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
A3P600L-FGG256
Manufacturer:
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Figure 2-25 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-174 • Minimum and Maximum DC Input and Output Levels
Table 2-175 • AC Waveforms, Measuring Points, and Capacitive Loads
OUTBUF_LVPECL
DC Parameter
VCCI
VOL
VOH
V
V
V
V
V
Input Low (V)
1.64
*
IL
ODIFF
OCM
ICM
IDIFF
Measuring point = V
, V
IH
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Supply Voltage
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
Output Low Voltage
Output High Voltage
FPGA
trip.
See
Description
Table 2-26 on page 2-25
N
P
Bourns Part Number: CAT16-PC4F12
100 Ω
100 Ω
Input High (V)
187 W
for a complete table of trip points.
1.94
0.625
1.762
Min.
0.96
1.01
300
R e v i s i o n 9
1.8
0
Z
Z
0
0
3.0
= 50 Ω
= 50 Ω
Max.
1.27
2.57
2.11
0.97
1.98
3.3
100 Ω
0.625
1.762
Min.
1.06
1.92
1.01
300
0
3.3
P
N
Max.
2.57
1.43
2.28
0.97
1.98
3.6
ProASIC3L Low Power Flash FPGAs
Measuring Point* (V)
FPGA
+
–
0.625
1.762
Min.
Cross point
1.30
2.13
1.01
300
0
3.6
INBUF_LVPECL
Figure
Max.
1.57
2.41
0.97
1.98
2.57
3.9
2-25. The
Units
mV
V
V
V
V
V
V
V
2- 97
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