A3P600L-FGG484 Actel, A3P600L-FGG484 Datasheet
A3P600L-FGG484
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A3P600L-FGG484 Summary of contents
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... SRAM and FIFO Configurations with Synchronous Operation: – 250 MHz: For 1.2 V systems – 350 MHz: For 1.5 V systems ® ARM Processor Support in ProASIC3L FPGAs • ARM Cortex™-M1 Soft Processor Available with or without Debug A3P600L M1A3P600L 600,000 13,824 36 108 Yes ...
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... Table 2 • ProASIC3L FPGAs Package Sizes Dimensions Package VQ100 Length × Width 14 × 14 (mm\mm) Nominal Area 196 2 (mm ) Pitch (mm) 0.5 Height (mm) 1. A3P600L A3P1000L M1A3P600L M1A3P1000L I/O Type Single- Differential Single- 4 Ended I/O I/O Pairs Ended I/O – – 154 35 154 ...
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... FG Package Type Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number ProASIC3L Devices A3P250L = 250,000 System Gates A3P600L = 600,000 System Gates A3P1000L = 1,000,000 System Gates A3PE3000L = 3,000,000 System Gates ProASIC3L Devices with Cortex-M1 M1A3P600L = 600,000 System Gates M1A3P1000L = 1,000,000 System Gates ...
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... I = Industrial temperature range: –40°C to 85°C ambient temperature. Speed Grade and Temperature Grade Matrix Temperature Grade Notes Commercial temperature range: 0°C to 70°C ambient temperature Industrial temperature range: –40°C to 85°C ambient temperature. http://www.actel.com/contact/default.aspx A3P250L A3P600L M1A3P600L C, I – – – – – ...
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... FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 ProASIC3L Low Power Flash FPGAs ...
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... ARM Cortex-M1 is available for free from Actel for use in M1 ProASIC3L FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support AES decryption. Flash*Freeze Technology The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which allows instantaneous switching from an active state to a static state ...
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... This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based ProASIC3L devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based ProASIC3L devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs ...
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... The versatility of the ProASIC3L core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming ...
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... ProASIC3L Device Family Overview Bank 0 ISP AES User Nonvolatile Decryption* FlashRom Bank 2 Figure 1-1 • ProASIC3L Device Architecture Overview with Four I/O Banks (A3P250L, A3P600L, and A3P1000L) ISP AES User Nonvolatile Decryption* FlashRom Figure 1-2 • ProASIC3EL Device Architecture Overview Flash*Freeze ...
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... Flash*Freeze Technology The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all SRAM and register information. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption ...
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... Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents ...
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... Wide Range I/O Support Actel ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1. ...
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ProASIC3L DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the ...
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ProASIC3L DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Ambient temperature A T Junction Temperature J 2 VCC 1.2 V–1.5 V wide range core voltage VJTAG JTAG DC voltage 3 VPUMP Programming voltage 6 VCCPLL Analog ...
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Table 2-4 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or Undershoot VCCI Duration as a Percentage of Clock Cycle 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at junction temperature at ...
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... ProASIC3L DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see 2 on page 2-5 for more details) ...
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VCC = VCCI + VT where VT can be from 0. 0.9 V (typically 0. VCC = 1.575 V Region 1: I/O Buffers are OFF VCC = 1.14 V Region 2: I/O buffers are ON. ...
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... A3P1000L 144 6.3 31.6 A3P250L 256 12.0 38.6 A3P600L 256 8.5 32.0 A3P1000L 256 6.6 28.1 AGLE3000 324 TBD TBD A3P600L 484 9.5 27.5 A3P1000L 484 8.0 23.3 A3PE3000L 484 4.7 20.6 A3PE3000L 896 2.4 13 Table 2-5. 100°C 70°C – ...
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... Characteristics, ProASIC3L Flash*Freeze Mode* DD A3P600L A3P1000L 0.33 0.55 0.88 ) Characteristics, ProASIC3L Sleep Mode (VCC = 0 V)* DD A3P250L A3P600L 1 1.5 V 1.7 1.7 1 1.5 V 1.8 1.8 1 1.5 V 1.9 1.9 1 1.5 V 2.2 2.2 1 1.5 V 2.5 2.5 ) Characteristics, Shutdown Mode (VCC, VCCI = 0 V) ...
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... To calculate total device I , multiply the number of banks used Includes VCC , VCCPLL, and VPUMP currents. 3. Per VCCI or VJTAG bank. 4. Values do not include I/O static contribution ( ProASIC3L Flash*Freeze Mode DD Core Voltage A3P250L A3P600L 1.2 V 0.33 0.55 1 1.5 V 1.7 1.7 1 1.5 V 1.8 1.8 1 ...
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Power per I/O Pin Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Pro I/O Banks Single-Ended 3.3 V LVTTL/LVCMOS 3.3 V LVTTL/LVCMOS – Schmitt trigger 2.5 V LVCMOS 2.5 V ...
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ProASIC3L DC and Switching Characteristics Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...
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Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Pro I/Os Single-Ended 3.3 V LVTTL/LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI ...
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ProASIC3L DC and Switching Characteristics Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...
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... AC13 * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero IDE. ProASIC3L Low Power Flash FPGAs Device Specific Dynamic Power (µW/MHz) A3PE3000L A3P1000L A3P600L A3P250L 12.61 9.28 2.66 1.59 0.56 0.07 ...
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... For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero IDE Device Specific Dynamic Power (µW/MHz) Definition A3PE3000L A3P1000L A3P600L A3P250L Device Specific Dynamic Power (µW) Definition A3PE3000L A3P1000L A3P600L A3P250L See See See R e visio n 9 19.7 14.50 12.80 11 ...
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... Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • ...
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ProASIC3L DC and Switching Characteristics Combinatorial Cells Contribution— C-CELL C-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in 1 page ...
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Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means that this net switches at ...
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ProASIC3L DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to Advanced I/O Banks only 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL Clock ...
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PY PAD t = MAX MAX(t DIN V trip PAD 50% Y GND t PY (R) DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example) t DIN CLK I/O Interface ...
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ProASIC3L DC and Switching Characteristics D CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example DOUT Q DOUT t = MAX MAX(t DOUT t ...
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EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip VOL D 50 EOUT (R) VCC 50% EOUT t ZLS PAD Vtrip VOL Figure ...
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ProASIC3L DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-22 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ...
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Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Advanced I/O Banks Drive Slew Min. I/O Standard Strength Rate V 3.3 V LVTTL / 12 mA ...
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ProASIC3L DC and Switching Characteristics Table 2-25 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS ...
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Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-26 • Summary of AC Memory Points Input Reference Voltage Standard (V 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-28 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI Pro I/O Banks Standard 3.3 V LVTTL / 12 mA High 3.3 V ...
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Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T Case VCCI Advanced I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 5pF 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI Pro I/O Banks Standard 3.3 V LVTTL / 12 mA High 3.3 V ...
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Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI Advanced I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 5pF 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High 5 ...
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ProASIC3L DC and Switching Characteristics Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI = 3.0 V Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 12 mA 3.3 V LVCMOS ...
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... PULL-DOWN Drive Strength Per PCI/PCI-X specification IBIS models located ) / I OHspec ProASIC3L Low Power Flash FPGAs R PULL- (Ω) (Ω) 100 300 50 150 100 200 50 100 200 225 100 112 200 224 100 112 TBD TBD – 14 – 12 – 15 – the Actel website ...
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... IBIS models located OLspec O H spec R e visio PULL-DOWN PULL- (Ω) (Ω) 100 300 100 300 50 150 50 150 100 300 100 300 50 150 50 150 100 200 100 200 50 100 50 100 200 224 100 112 TBD TBD the Actel website at ...
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... IBIS models located spec ProASIC3L Low Power Flash FPGAs R R PULL-DOWN PULL- (Ω) (Ω) 100 300 100 300 50 150 50 150 100 200 100 200 50 100 50 100 25 50 200 225 100 112 200 224 100 112 TBD TBD 25 75 the Actel website ...
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ProASIC3L DC and Switching Characteristics Table 2-38 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values VCCI Min 1.2 V LVCMOS ...
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Table 2-39 • I/O Short Currents I OSH Applicable to Pro I/Os 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCIX 3.3 V GTL 2.5 V GTL ...
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ProASIC3L DC and Switching Characteristics Table 2-40 • I/O Short Currents I Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI-X * ...
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Table 2-41 • I/O Short Currents I OSH Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI 100°C ...
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... The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low voltage transistor–transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V ...
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ProASIC3L DC and Switching Characteristics Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL Min. Max. Drive Strength –0.3 0.8 ...
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Timing Characteristics 1 Core Voltage Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t ...
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ProASIC3L DC and Switching Characteristics Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT ...
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Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed ...
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Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.70 ...
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ProASIC3L DC and Switching Characteristics Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t ...
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V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-62 • Minimum and Maximum ...
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ProASIC3L DC and Switching Characteristics Table 2-64 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS VIL Drive Min. Max. Strength –0.3 0 –0.3 0.7 ...
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Timing Characteristics 1 Core Voltage Table 2-66 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade DOUT DP ...
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ProASIC3L DC and Switching Characteristics Table 2-68 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 4 mA Std. 0.54 ...
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Table 2-70 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.54 5.27 –1 0.46 ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-72 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t ...
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Table 2-74 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT Std. 0.70 5.79 –1 0.60 4.92 6 ...
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ProASIC3L DC and Switching Characteristics Table 2-76 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/Os Drive Speed Strength Grade t t DOUT 4 mA Std. 0.70 ...
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V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-78 • Minimum and ...
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ProASIC3L DC and Switching Characteristics Table 2-80 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS VIL Drive Min. Max. Strength –0.3 0.35 * VCCI 0.65 ...
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Timing Characteristics 1 Core Voltage Table 2-82 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade DOUT DP ...
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ProASIC3L DC and Switching Characteristics Table 2-84 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. 0.54 ...
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Table 2-86 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.54 7.21 –1 0.46 ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-88 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t ...
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Table 2-90 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.70 7.77 –1 0.60 6.61 ...
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ProASIC3L DC and Switching Characteristics Table 2-92 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. ...
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V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-94 • Minimum ...
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ProASIC3L DC and Switching Characteristics Table 2-96 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL Drive Min. Max. Strength –0.3 0.35 * VCCI 0.65 * ...
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Timing Characteristics 1 Core Voltage Table 2-98 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade DOUT DP ...
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ProASIC3L DC and Switching Characteristics Table 2-100 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. 0.54 ...
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Table 2-102 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.54 7.32 –1 0.46 ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-104 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t ...
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Table 2-106 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.70 8.00 –1 0.60 6.80 ...
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ProASIC3L DC and Switching Characteristics Table 2-108 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. ...
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V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-110 • Minimum and Maximum DC ...
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ProASIC3L DC and Switching Characteristics Test Point Datapath Figure 2-11 • AC Loading Table 2-113 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low ( Measuring point = V See Table 2-26 on page 2-25 trip. 2- ...
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Timing Characteristics 1 Core Voltage Table 2-114 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.77 11.80 0.05 2.38 –1 0.66 ...
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ProASIC3L DC and Switching Characteristics Table 2-119 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Strength Speed Grade Std. –1 Notes: 1. Software default selection highlighted in gray. 2. ...
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... Per PCI specification Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the database; Actel loadings for enable path characterization are described VCCI for ...
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ProASIC3L DC and Switching Characteristics Table 2-123 • 3.3 V PCI/PCI-X – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Speed Grade DOUT DP Std. 0.54 2.41 0.04 –1 0.46 ...
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Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-128 • Minimum and Maximum DC Input and Output Levels ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-130 • 3.3 V GTL – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade ...
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V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-132 • Minimum and Maximum DC Input and Output Levels 2.5 GTL VIL ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-134 • 2.5 V GTL – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade ...
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V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-136 • Minimum and Maximum DC Input and Output Levels 3.3 V ...
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ProASIC3L DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-140 • Minimum and Maximum DC Input ...
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Timing Characteristics Table 2-142 • 2.5 V GTL+ – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 2.3 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade DOUT DP ...
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ProASIC3L DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-144 • ...
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Timing Characteristics Table 2-146 • HSTL Class I – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade DOUT DP ...
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ProASIC3L DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-148 • ...
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Timing Characteristics Table 2-150 • HSTL Class II – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade DOUT DP ...
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ProASIC3L DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-152 • Minimum and ...
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Timing Characteristics Table 2-154 • SSTL2 Class I – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/Os Speed Grade DOUT DP DIN ...
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ProASIC3L DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-156 • Minimum and ...
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SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-160 • Minimum and Maximum DC Input and Output ...
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ProASIC3L DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-164 • Minimum and ...
Page 107
... Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards ...
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ProASIC3L DC and Switching Characteristics Table 2-168 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH ODIFF V OCM V ...
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Timing Characteristics 1 Core Voltage Table 2-170 • LVDS – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Speed Grade t DOUT Std. 0.59 –1 0.50 Note: For specific junction temperature ...
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... These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in ...
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LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-176 • LVPECL – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Speed Grade t DOUT Std. 0.59 –1 0.50 ...
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I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset PRE Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-26 • ...
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ProASIC3L DC and Switching Characteristics Table 2-180 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-27 • Timing Model of ...
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ProASIC3L DC and Switching Characteristics Table 2-181 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...
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Input Register 50% 50% CLK t ISUD 1 50% Data Enable 50% t IHE t ISUE Preset Clear Out_1 Figure 2-28 • Input Register Timing Diagram 50% 50% t IHD 0 50 IWPRE IRECPRE 50% 50 ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-182 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Input Data Register ICLKQ t Data Setup Time for the Input Data ...
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Output Register 50% 50% CLK t 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-29 • Output Register Timing Diagram 50% 50% t OSUD OHD 0 50 OWPRE ORECPRE 50% 50 ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-184 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data ...
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Output Enable Register 50% 50% CLK t OESUD 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-30 • Output Enable Register Timing Diagram 50% 50% t OEHD 50 OEWPRE t OERECPRE 50% ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-186 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-31 • Input DDR Timing Model Table 2-188 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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ProASIC3L DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-32 • Input DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-189 • Input DDR Propagation Delays Commercial-Case ...
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V DC Core Voltage Table 2-190 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR DDRICLKQ2 t Data Setup for Input DDR (fall) DDRISUD1 t Data ...
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ProASIC3L DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-33 • Output DDR Timing Model Table 2-191 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t ...
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CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-34 • Output DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-192 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-193 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for Output DDR DDROCLKQ t Data_F Data Setup for Output DDR DDRISUD1 t Data_R Data ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the and ProASIC3 Macro ...
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ProASIC3L DC and Switching Characteristics OUT GND VCC OUT Figure 2-36 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX(t PD PD(RR) where edges are applicable ...
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Timing Characteristics 1 Core Voltage Table 2-194 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell Equation INV Y =!A AND2 · B NAND2 Y =!(A · B) OR2 ...
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ProASIC3L DC and Switching Characteristics VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-38 • Timing Model and Waveforms Timing Characteristics 1 Core Voltage Table 2-196 • Register Delays Commercial-Case Conditions: T ...
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ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-197 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time for ...
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Global Resource Characteristics A3P250L Clock Tree Topology Clock delays are device-specific. global tree presented in Figure 2- used to drive all D-flip-flops in the device. CCC Figure 2-39 • Example of Global Tree Use in an A3P250L Device ...
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ProASIC3L DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the ...
Page 137
... Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to values. Table 2-201 • A3P600L Global Resource – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter Description ...
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ProASIC3L DC and Switching Characteristics Table 2-202 • A3P1000L Global Resource – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t ...
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Table 2-204 • A3PE3000L Global Resource – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High ...
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ProASIC3L DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-206 • ProASIC3LP CCC/PLL Specification CCC/PLL Operating at 1.2 V Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in ...
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Table 2-207 • ProASIC3LP CCC/PLL Specification CCC/PLL Operating at 1.5 V Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f 4 Serial Clock (SCLK) for Dynamic PLL Delay Increments in Programmable Delay Blocks Number of Programmable ...
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ProASIC3L DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-41 • RAM Models RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA ...
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Timing Waveforms t CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-42 • RAM Read for Pass-Through Output t CYC t CKH CLK ...
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ProASIC3L DC and Switching Characteristics CLK t AS ADD t BKS BLK_B t ENS WEN_B Figure 2-44 • RAM Write, Output Retained (WMODE = 0) CLK ADD BLK_B WEN_B (pass-through) DO (pipelined) Figure 2-45 ...
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CLK1 ADD1 DI1 1 t CCKH CLK2 WEN_B1 WEN_B2 A ADD2 0 DI2 D 0 DO2 D n (pass-through) DO2 D (pipelined) n Figure 2-46 • Write Access after ...
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ProASIC3L DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-47 • Read Access after Write onto Same Address ...
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CLK1 ADD1 A 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A 0 DI2 D 1 WEN_B2 Figure 2-48 • Write Access after Read onto Same Address t ...
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ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-208 • RAM4K9 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t ...
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Table 2-209 • RAM4K9 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B ...
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ProASIC3L DC and Switching Characteristics Table 2-210 • RAM512X18 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B ...
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Table 2-211 • RAM512X18 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input ...
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ProASIC3L DC and Switching Characteristics FIFO Figure 2-50 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-51 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Assertion t ...
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ProASIC3L DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-53 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...
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Timing Characteristics Table 2-212 • FIFO – Applies to 1 Core Voltage Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time ...
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ProASIC3L DC and Switching Characteristics Table 2-213 • FIFO – Applies to 1 Core Voltage Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t ...
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Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-56 • Timing Diagram Timing Characteristics Table 2-214 • Embedded FlashROM Access Time – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address ...
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ProASIC3L DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" section ...
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... Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3L Low Power Flash FPGAs ...
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Package Pin Assignments 100-Pin VQFP Pin Number A3P250L Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO112PSB3 9 GND 10 GFB1/IO109PDB3 11 GFB0/IO109NDB3 12 VCOMPLF 13 GFA0/IO108NPB3 14 VCCPLF 15 GFA1/IO108PPB3 16 ...
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... PQFP 208 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3L Low Power Flash FPGAs 208-Pin PQFP ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PL250 Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO115UDB3 9 IO115VDB3 10 IO114UDB3 11 IO114VDB3 12 IO113PDB3 13 IO113NDB3 14 IO112PDB3 15 IO112NDB3 16 ...
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PQFP Pin Number A3PL250 Function 109 TRST 110 VJTAG 111 GDA0/IO60VDB1 112 GDA1/IO60UDB1 113 GDB0/IO59VDB1 114 GDB1/IO59UDB1 115 GDC0/IO58VDB1 116 GDC1/IO58UDB1 117 IO57VDB1 118 IO57UDB1 119 IO56NDB1 120 IO56PDB1 121 IO55RSB1 122 GND 123 VCCIB1 124 NC 125 NC ...
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Package Pin Assignments 208-Pin PQFP Pin Number A3PL600 Function 1 GND 2 GAA2/IO174PDB3 3 IO174NDB3 4 GAB2/IO173PDB3 5 IO173NDB3 6 GAC2/IO172PDB3 7 IO172NDB3 8 IO171PDB3 9 IO171NDB3 10 IO170PDB3 11 IO170NDB3 12 IO169PDB3 13 IO169NDB3 14 IO168PDB3 15 IO168NDB3 16 ...
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PQFP Pin Number A3PL600 Function 108 TDO 109 TRST 110 VJTAG 111 GDA0/IO88NDB1 112 GDA1/IO88PDB1 113 GDB0/IO87NDB1 114 GDB1/IO87PDB1 115 GDC0/IO86NDB1 116 GDC1/IO86PDB1 117 IO84NDB1 118 IO84PDB1 119 IO82NDB1 120 IO82PDB1 121 IO81PSB1 122 GND 123 VCCIB1 124 IO77NDB1 ...
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Package Pin Assignments 208-Pin PQFP Pin Number APL1000 Function 1 GND 2 GAA2/IO225PDB3 3 IO225NDB3 4 GAB2/IO224PDB3 5 IO224NDB3 6 GAC2/IO223PDB3 7 IO223NDB3 8 IO222PDB3 9 IO222NDB3 10 IO220PDB3 11 IO220NDB3 12 IO218PDB3 13 IO218NDB3 14 IO216PDB3 15 IO216NDB3 16 ...
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PQFP Pin Number APL1000 Function 108 TDO 109 TRST 110 VJTAG 111 GDA0/IO113NDB1 112 GDA1/IO113PDB1 113 GDB0/IO112NDB1 114 GDB1/IO112PDB1 115 GDC0/IO111NDB1 116 GDC1/IO111PDB1 117 IO109NDB1 118 IO109PDB1 119 IO106NDB1 120 IO106PDB1 121 IO104PSB1 122 GND 123 VCCIB1 124 IO99NDB1 ...
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Package Pin Assignments 208-Pin PQFP Pin A3PE3000L Number Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO308PSB7V4 5 GAA2/IO309PDB7V4 6 IO309NDB7V4 7 GAC2/IO307PDB7V4 8 IO307NDB7V4 9 IO303PDB7V3 10 IO303NDB7V3 11 IO299PDB7V3 12 IO299NDB7V3 13 IO295PDB7V2 14 IO295NDB7V2 15 IO291PSB7V2 16 ...
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PQFP Pin A3PE3000L Number Function 106 VPUMP 107 GNDQ 108 TDO 109 TRST 110 VJTAG 111 VMV3 112 GDA0/IO153NPB3V4 113 GDB0/IO152NPB3V4 114 GDA1/IO153PPB3V4 115 GDB1/IO152PPB3V4 116 GDC0/IO151NDB3V4 117 GDC1/IO151PDB3V4 118 IO134NDB3V2 119 IO134PDB3V2 120 IO132NDB3V2 121 IO132PDB3V2 122 GND ...
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... Package Pin Assignments 144-Pin FBGA 12 11 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...
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FBGA Pin Number A3P250L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO29RSB0 A8 VCC A9 IO33RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO117UDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO14RSB0 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P250L Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO96RSB2 L4 ...
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... F2 VCOMPLF F3 GFB1/IO163PPB3 F4 IO161NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO69NDB1 F9 GCB0/IO70NPB1 F10 GND F11 GCA1/IO71PDB1 F12 GCA2/IO72PDB1 ProASIC3L Low Power Flash FPGAs 144-Pin FBGA Pin Number A3P600L Function G1 GFA1/IO162PPB3 G2 GND G3 VCCPLF G4 GFA0/IO162NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO86PPB1 G9 IO74NDB1 G10 GCC2/IO74PDB1 G11 IO73NDB1 G12 GCB2/IO73PDB1 H1 VCC ...
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... GDB0/IO87NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO142RSB 2 L4 IO136RSB2 L5 VCCIB2 L6 IO115RSB2 L7 IO103RSB2 L8 IO97RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO141RSB2 M3 IO138RSB2 M4 IO123RSB2 M5 IO126RSB2 M6 IO134RSB2 M7 IO108RSB2 M8 IO99RSB2 M9 TDI M10 VCCIB2 3- 16 144-Pin FBGA Pin Number A3P600L Function M11 VPUMP M12 GNDQ R e visio n 9 ...
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FBGA Pin Number A3P1000L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO44RSB0 A8 VCC A9 IO69RSB0 A10 GBA0/IO76RSB0 A11 GBA1/IO77RSB0 A12 GNDQ B1 GAB2/IO224PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO13RSB0 ...
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Package Pin Assignments 144-Pin FBGA Pin Number A3P1000L Function K1 GEB0/IO189NDB3 K2 GEA1/IO188PDB3 K3 GEA0/IO188NDB3 K4 GEA2/IO187RSB2 K5 IO169RSB2 K6 IO152RSB2 K7 GND K8 IO117RSB2 K9 GDC2/IO116RSB2 K10 GND K11 GDA0/IO113NDB1 K12 GDB0/IO112NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO186RSB 2 ...
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... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ProASIC3L Low Power Flash FPGAs ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P250L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO07RSB0 A6 IO10RSB0 A7 IO11RSB0 A8 IO15RSB0 A9 IO20RSB0 A10 IO25RSB0 A11 IO29RSB0 A12 IO33RSB0 A13 GBB1/IO38RSB0 A14 GBA0/IO39RSB0 A15 GBA1/IO40RSB0 A16 ...
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FBGA Pin Number A3P250L Function G13 GCC1/IO48PPB1 G14 IO47NPB1 G15 IO54PDB1 G16 IO54NDB1 H1 GFB0/IO109NPB3 H2 GFA0/IO108NDB3 H3 GFB1/IO109PPB3 H4 VCOMPLF H5 GFC0/IO110NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO48NPB1 H13 GCB1/IO49PPB1 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P250L Function P9 IO76RSB2 P10 IO71RSB2 P11 IO66RSB2 P12 NC P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO60VDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 R8 ...
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... D15 IO53RSB0 D16 IO63NDB1 E1 IO166PDB3 E2 IO167NPB3 E3 IO172NDB3 E4 IO169NDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO25RSB0 ProASIC3L Low Power Flash FPGAs 256-Pin FBGA Pin Number A3P600L Function E9 IO31RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO62PDB1 E14 IO67PPB1 E15 IO64PPB1 E16 IO66PDB1 F1 IO166NDB3 F2 IO168NPB3 F3 IO167PPB3 F4 ...
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... GND L12 VCCIB1 L13 GDB0/IO87NPB1 L14 IO85NDB1 L15 IO85PDB1 L16 IO84PDB1 M1 IO150PDB3 M2 IO151NPB3 M3 IO147NPB3 M4 GEC0/IO146NPB3 R e visio n 9 256-Pin FBGA Pin Number A3P600L Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 IO117RSB2 M9 IO110RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 IO94RSB2 M14 GDB1/IO87PPB1 M15 GDC1/IO86PDB1 ...
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... TDI R15 GNDQ R16 TDO T1 GND T2 IO137RSB2 T3 FF/GEB2/IO142RSB 2 T4 IO134RSB2 T5 IO125RSB2 T6 IO123RSB2 T7 IO118RSB2 T8 IO115RSB2 T9 IO111RSB2 T10 IO106RSB2 T11 IO102RSB2 256-Pin FBGA Pin Number A3P600L Function T12 GDC2/IO91RSB2 T13 IO93RSB2 T14 GDA2/IO89RSB2 T15 TMS T16 GND ProASIC3L Low Power Flash FPGAs 3- 25 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P1000L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO16RSB0 A6 IO22RSB0 A7 IO28RSB0 A8 IO35RSB0 A9 IO45RSB0 A10 IO50RSB0 A11 IO55RSB0 A12 IO61RSB0 A13 GBB1/IO75RSB0 A14 GBA0/IO76RSB0 A15 GBA1/IO77RSB0 A16 ...
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FBGA Pin Number A3P1000L Function G13 GCC1/IO91PPB1 G14 IO90NPB1 G15 IO88PDB1 G16 IO88NDB1 H1 GFB0/IO208NPB3 H2 GFA0/IO207NDB3 H3 GFB1/IO208PPB3 H4 VCOMPLF H5 GFC0/IO209NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO91NPB1 H13 GCB1/IO92PPB1 ...
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Package Pin Assignments 256-Pin FBGA Pin Number A3P1000L Function P9 IO137RSB2 P10 IO134RSB2 P11 IO128RSB2 P12 VMV1 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO113NDB1 R1 GEA1/IO188PDB3 R2 GEA0/IO188NDB3 R3 IO184RSB2 R4 GEC2/IO185RSB2 R5 IO168RSB2 R6 IO163RSB2 R7 IO157RSB2 R8 ...
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... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ProASIC3L Low Power Flash FPGAs ...
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Package Pin Assignments 324-Pin FBGA A3PE3000L Pin Number Function A1 GND A2 IO08NDB0V0 A3 IO08PDB0V0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO12PDB0V1 A7 GND A8 IO32NDB0V3 A9 IO32PDB0V3 A10 IO42PPB1V0 A11 IO52NPB1V1 A12 GND A13 IO66NDB1V3 A14 IO72NDB1V3 A15 IO72PDB1V3 A16 ...
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FBGA A3PE3000L Pin Number Function F12 IO58PDB1V2 F13 IO94PPB2V1 F14 VCOMPLB F15 GBC2/IO84PDB2V0 F16 IO84NDB2V0 F17 IO92NDB2V1 F18 IO92PDB2V1 G1 GND G2 IO287PDB7V1 G3 IO287NDB7V1 G4 IO283PPB7V1 G5 VCCIB7 G6 IO279PDB7V0 G7 IO291NPB7V2 G8 VCC G9 IO26NDB0V3 G10 IO34NDB0V4 ...
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Package Pin Assignments 324-Pin FBGA A3PE3000L Pin Number Function M9 IO192PPB4V4 M10 IO154NPB4V0 M11 VCC M12 GDA0/IO153NPB3V4 M13 IO132NDB3V2 M14 VCCIB3 M15 IO134NDB3V2 M16 IO134PDB3V2 M17 IO128PPB3V1 M18 GND N1 IO247NDB6V1 N2 IO247PDB6V1 N3 IO251NPB6V2 N4 GEC0/IO236NDB6V0 N5 VCOMPLE N6 ...
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FBGA A3PE3000L Pin Number Function V1 GND V2 IO218NDB5V3 V3 IO218PDB5V3 V4 IO206NDB5V1 V5 IO206PDB5V1 V6 IO198NPB5V0 V7 GND V8 IO190NDB4V4 V9 IO190PDB4V4 V10 IO182PPB4V3 V11 IO180PPB4V3 V12 GND V13 IO162NDB4V1 V14 IO160NDB4V0 V15 IO160PDB4V0 V16 IO158NDB4V0 V17 IO158PDB4V0 ...
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... Package Pin Assignments 484-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...
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... IO100RSB2 AB17 IO95RSB2 AB18 NC AB19 NC AB20 VCCIB2 AB21 GND AB22 GND B1 GND B2 VCCIB3 IO08RSB0 ProASIC3L Low Power Flash FPGAs 484-Pin FBGA Pin Number A3P600L Function B7 IO12RSB0 B10 IO17RSB0 B11 NC B12 NC B13 IO36RSB0 B14 NC B15 NC B16 IO47RSB0 B17 IO49RSB0 B18 NC B19 NC B20 NC ...
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... IO51RSB0 F17 VMV0 F18 IO61NPB1 F19 IO63PDB1 F20 NC F21 NC F22 NC G1 IO170NDB3 G2 IO170PDB3 IO171NDB3 R e visio n 9 484-Pin FBGA Pin Number A3P600L Function G5 IO171PDB3 G6 GAC2/IO172PDB3 G7 IO06RSB0 G8 GNDQ G9 IO10RSB0 G10 IO19RSB0 G11 IO26RSB0 G12 IO30RSB0 G13 IO40RSB0 G14 IO45RSB0 G15 GNDQ G16 ...
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... L16 GCB1/IO70PPB1 L17 GCA0/IO71NPB1 L18 IO67NPB1 L19 GCB0/IO70NPB1 L20 IO77PDB1 L21 IO77NDB1 L22 IO78NPB1 IO155NDB3 ProASIC3L Low Power Flash FPGAs 484-Pin FBGA Pin Number A3P600L Function M3 IO158NPB3 M4 GFA2/IO161PPB3 M5 GFA1/IO162PDB3 M6 VCCPLF M7 IO160NDB3 M8 GFB2/IO160PDB3 M9 VCC M10 GND M11 GND M12 GND M13 GND ...
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... T13 IO103RSB2 T14 IO99RSB2 T15 GNDQ T16 IO92RSB2 T17 VJTAG T18 GDC0/IO86NDB1 T19 GDA1/IO88PDB1 T20 NC T21 IO83PDB1 T22 IO82NDB1 R e visio n 9 484-Pin FBGA Pin Number A3P600L Function U1 IO149PDB3 U2 IO149NDB3 GEB1/IO145PDB3 U5 GEB0/IO145NDB3 U6 VMV2 U7 IO138RSB2 U8 IO136RSB2 U9 IO131RSB2 U10 IO124RSB2 U11 IO119RSB2 U12 ...
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... W14 IO102RSB2 W15 GDC2/IO91RSB2 W16 IO93RSB2 W17 GDA2/IO89RSB2 W18 TMS W19 GND W20 NC W21 NC W22 NC Y1 VCCIB3 Y2 IO148NDB3 GND 484-Pin FBGA Pin Number A3P600L Function VCC Y9 VCC Y10 NC Y11 NC Y12 NC Y13 NC Y14 VCC Y15 VCC Y16 NC Y17 NC Y18 GND Y19 NC Y20 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3P1000L Function A1 GND A2 GND A3 VCCIB0 A4 IO07RSB0 A5 IO09RSB0 A6 IO13RSB0 A7 IO18RSB0 A8 IO20RSB0 A9 IO26RSB0 A10 IO32RSB0 A11 IO40RSB0 A12 IO41RSB0 A13 IO53RSB0 A14 IO59RSB0 A15 IO64RSB0 A16 ...
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FBGA Pin Number A3P1000L Function C21 NC C22 VCCIB1 D1 IO219PDB3 D2 IO220NDB3 GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 D7 GAB0/IO02RSB0 D8 IO16RSB0 D9 IO22RSB0 D10 IO28RSB0 D11 IO35RSB0 D12 IO45RSB0 D13 IO50RSB0 D14 IO55RSB0 D15 IO61RSB0 ...
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Package Pin Assignments 484-Pin FBGA Pin Number A3P1000L Function H19 IO87PDB1 H20 VCC H21 NC H22 NC J1 IO212NDB3 J2 IO212PDB3 IO217NDB3 J5 IO218NDB3 J6 IO216PDB3 J7 IO216NDB3 J8 VCCIB3 J9 GND J10 VCC J11 VCC J12 ...