APA300-PQ208I Actel, APA300-PQ208I Datasheet - Page 82

• Manufacturer Part Number: APA300-PQ208I
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-PQ208I

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 5 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIFO Reset
Notes:
1. During reset, either the enables (WRB and RBD) OR the clocks (WCLKS and RCKLS) must be low.
2. The plot shows the normal operation status.
Figure 2-45 • FIFO Reset
Table 2-68 • T
2 -7 2
Symbol t
CBRSH
CBRSS
ERSA
FRSA
RSL
THRSA
WBRSH
WBRSS
Note: During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.
ProASIC
1
1
1
1
PLUS
xxx
T
J
J
Flash Family FPGAs
= 0°C to 110°C; V
= –55°C to 150°C, V
WCLKS or RCLKS ↑ hold from RESETB ↑
WCLKS or RCLKS ↓ setup to RESETB ↑
New EMPTY ↑ access from RESETB ↓
FULL ↓ access from RESETB ↓
RESETB low phase
EQTH or GETH access from RESETB ↓
WB ↓ hold from RESETB ↑
WB ↑ setup to RESETB ↑
WCLKS, RCLKS
EQTH, GETH
t ERSA , t FRSA
WRB/RBD
RESETB
DD
EMPTY
Description
t THRSA
FULL
DD
= 2.3 V to 2.7 V for Commercial/Industrial
1
1
= 2.3 V to 2.7 V for Military/MIL-STD-883
t CBRSS
v5.9
t RSL
Min.
1.5
1.5
3.0
3.0
7.5
4.5
1.5
1.5
Max.
t WBRSS
Units
ns
ns
ns
ns
ns
ns
ns
ns
t WBRSH
Cycle Start
Cycle Start
t CBRSH
Synchronous mode only
Synchronous mode only
Asynchronous mode only
Asynchronous mode only
Notes