AGL125V2-FGG144 Actel, AGL125V2-FGG144 Datasheet - Page 148
![FPGA - Field Programmable Gate Array 125K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL125V2-FGG144
Manufacturer Part Number
AGL125V2-FGG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL125V2-FGG144
Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL125V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
ON
Quantity:
20 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL125V2-FGG144I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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IGLOO DC and Switching Characteristics
JTAG 1532 Characteristics
Table 2-198 • JTAG 1532
Table 2-199 • JTAG 1532
2- 13 4
Parameter
t
t
t
t
t
t
F
t
t
t
Note:
Parameter
t
t
t
t
t
t
F
t
t
t
Note:
DISU
DIHD
TMSSU
TMDHD
TCK2Q
RSTB2Q
TRSTREM
TRSTREC
TRSTMPW
DISU
DIHD
TMSSU
TMDHD
TCK2Q
RSTB2Q
TRSTREM
TRSTREC
TRSTMPW
TCKMAX
TCKMAX
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the
Characteristics" section on page 2-20
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
Reset to Q (data out)
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
Reset to Q (data out)
TCK Maximum Frequency
ResetB Removal Time
ResetB Recovery Time
ResetB Minimum Pulse
J
J
= 70°C, Worst-Case VCC = 1.425 V
= 70°C, Worst-Case VCC = 1.14 V
for more details.
Description
Description
R ev isio n 1 8
Table 2-6 on page 2-7
Table 2-6 on page 2-7
25.00
TBD
2.00
1.00
2.00
8.00
0.58
0.00
Std.
1.00
11.00
30.00
15
TBD
Std.
1.50
3.00
1.50
3.00
9.00
1.18
0.00
for derating values.
for derating values.
"User I/O
Units
MHz
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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