AGL125V2-FGG144 Actel, AGL125V2-FGG144 Datasheet - Page 101
![FPGA - Field Programmable Gate Array 125K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL125V2-FGG144
Manufacturer Part Number
AGL125V2-FGG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL125V2-FGG144
Processor Series
AGL125
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
125 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL125V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
ON
Quantity:
20 000
Company:
Part Number:
AGL125V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL125V2-FGG144I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
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Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Enable
Data
CLK
CLR
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
CC
Data Input I/O Register with
BB
AA
DD
Active High Enable
Active High Clear
Positive-Edge Triggered
D
E
DFN1E1C1
CLR
Q
EE
INBUF
Y
R ev i si o n 1 8
Array
Core
INBUF
CLKBUF
Data_out
LL
HH
JJ
KK
GG
FF
Data Output Register and
Enable Output Register with
D
E
D
E
DFN1E1C1
DFN1E1C1
IGLOO Low Power Flash FPGAs
Active High Enable
Active High Clear
Positive-Edge Triggered
CLR
CLR
Q
Q
DOUT
EOUT
2- 87
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