LFXP2-30E-5FN484C Lattice, LFXP2-30E-5FN484C Datasheet - Page 244
![FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd
Manufacturer
Lattice
Specifications of LFXP2-30E-5FN484C
Number Of Macrocells
29000
Number Of Programmable I/os
363
Data Ram Size
396288
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
• www.infinion.com, DDR SDRAM Data Sheets
• www.samsung.com, DDR SDRAM Data Sheets
• www.toshiba.com, DDR FCRAM Data Sheet
• www.fujitsu.com, DDR FCRAM Data Sheet
• RD1019,
• IPUG35,
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
Revision History
February 2007
February 2009
June 2009
May 2007
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
www.latticesemi.com
Date
DDR1 & DDR2 SDRAM Controller (Pipelined Versions) User’s Guide
QDR Memory Controller Reference Design
Version
01.0
01.1
01.2
01.3
Initial release.
Updated the port names on the input DDR block diagrams.
Updated text in DQS Transition Detect section under Memory Read
Implementation.
Updated DLL Compensated DQS Delay Elements text section.
Updated DQSDLL Update Control text section.
11-40
LatticeXP2 High-Speed I/O Interface
Change Summary
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