LFXP2-30E-5FN484C Lattice, LFXP2-30E-5FN484C Datasheet - Page 114
![FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd
Manufacturer
Lattice
Specifications of LFXP2-30E-5FN484C
Number Of Macrocells
29000
Number Of Programmable I/os
363
Data Ram Size
396288
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 114 of 341
- Download datasheet (10Mb)
Lattice Semiconductor
FIXEDDELAY
The FIXEDDELAY attribute is available to each input pin. This attribute, when enabled, is used to achieve zero hold
time for the input registers when using global clock. This attribute can only be assigned in the HDL source.
Values: TRUE, FALSE
Default: FALSE
INBUF
By default, all the unused input buffers are disabled. The INBUF attribute is used to enable the unused input buffers
when performing a boundary scan test. This is a global attribute and can be globally set to ON or OFF.
Values: ON, OFF
Default: ON
DIN/DOUT
This attribute can be used to assign I/O registers. Using DIN will assert an input register and using the DOUT attri-
bute will assert an output register. By default, the software will try to assign the I/O registers, if applicable. The user
can turn this OFF by using the synthesis attribute or by using the Spreadsheet view of the Design Planner. These
attributes can only be applied to registers.
LOC
This attribute can be used to make pin assignments to the I/O ports in the design. This attributes is only used when
the pin assignments are made in HDL source. Designers can also assign pins directly using the Spreadsheet view
of the Design Planner in the ispLEVER software. The appendices explain this in further detail.
Design Considerations and Usage
This section discusses some of the design rules and considerations that must be taken into account when design-
ing with the LatticeXP2 sysIO buffer
Banking Rules
• If V
• If V
• When implementing DDR memory interfaces, the V
• Only the top and bottom banks (banks 0, 1, 4 and 5)) will support PCI clamps.
• All legal input buffers should be independent of bank V
Differential I/O Rules
• All banks can support LVDS input buffers. Only the banks on the right and left sides (Banks 2, 3, 6 and 7) will
• All banks support emulated differential buffers using external resistor pack and complementary LVCMOS drivers.
• Only 50% of the I/Os on the left and right sides can provide LVDS output buffer capability. LVDS can only be
V
V
pins and cannot be used to power any other referenced inputs.
bank V
support True Differential output buffers. The banks on all sides will support the LVDS input buffers. The user can
use emulated LVDS output buffers on these banks.
assigned to the TRUE pad. The ispLEVER design tool will automatically assign the other I/Os of the differential
pair to the complementary pad. Refer to the device data sheet to see the pin listings for all LVDS pairs.
CCAUX,
CC
CCIO
CCIO
, thus minimizing leakage.
CCIO
or V
or V
thus minimizing leakage.
of 1.8V and 1.5V.
CCJ
CCJ
for any bank is set to 3.3 V, it is recommended that it be connected to the same power supply as
for any bank is set to 1.2V, it is recommended that it be connected to the same power supply as
REF1
8-10
CCIO,
of the bank is used to provide reference to the interface
except for 1.8V and 1.5V buffers, which require a
LatticeXP2 sysIO Usage Guide
Related parts for LFXP2-30E-5FN484C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LFXP2-30E-6FTN256I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeXP2 Family 29000 Cells Flash Technology 1.2V 256-Pin FTBGA
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP2-30E-6FTN256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 30KLUTS 201I/O 256FTBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5FTN256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 30KLUTS 201I/O 256FTBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-6FN484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 30KLUTS 363I/O 484FPBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5FN484I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 30KLUTS 363I/O 484FPBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-6FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 30KLUTS 472I/O 672FPBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5FN672I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC DSP 30KLUTS 472I/O 672FPBGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5FT256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 201I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5FTN256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 201I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5F672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 472I/O 672-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5FN672C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 472I/O 672-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5FT256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 201I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-6FT256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 201I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-7FTN256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 201I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP2-30E-5F672I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 30KLUTS 472I/O 672-BGA
Manufacturer:
Lattice
Datasheet: