AGL600V2-FGG144 Actel, AGL600V2-FGG144 Datasheet - Page 45
![FPGA - Field Programmable Gate Array 600K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL600V2-FGG144
Manufacturer Part Number
AGL600V2-FGG144
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL600V2-FGG144
Processor Series
AGL600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL600V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL600V2-FGG144I
Manufacturer:
ACTEL
Quantity:
101
Company:
Part Number:
AGL600V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
3.3 V
LVTTL /
3.3 V
LVCMOS
3.3 V
LVCMOS
Wide
Range
2.5 V
LVCMOS
1.8 V
LVCMOS
1.5 V
LVCMOS
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to
equivalent software default drive strength. These values are for normal ranges only.
2
100 µA
Commercial-Case Conditions: T
standard)
Applicable to Standard I/O Banks
8 mA
8 mA
4 mA
2 mA
8
8
8
4
2
High
High
High
High
High
5
5
5
5
5
J
–
–
–
–
–
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per
0.97
0.97
0.97
0.97
0.97
R ev i si o n 1 8
μ
A drive strength only. The configuration will not operate at the
1.85
2.62
1.88
2.18
2.51
0.18
0.18
0.18
0.18
0.18
Table 2-6 on page 2-7
0.83
1.17
1.04
0.98
1.14
0.66 1.89 1.46
0.66 2.63 2.02
0.66 1.92 1.63
0.66 2.22 1.93
0.66 2.56 2.21
IGLOO Low Power Flash FPGAs
for derating values.
1.96
2.79
1.95
1.97
1.99
2.26
3.17
2.15
2.06
2.03
2- 31
ns
ns
ns
ns
ns
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