AGL600V2-FGG144 Actel, AGL600V2-FGG144 Datasheet - Page 26
![FPGA - Field Programmable Gate Array 600K System Gates](/photos/16/15/161502/landingpageacteligloofpga_sml.jpg)
AGL600V2-FGG144
Manufacturer Part Number
AGL600V2-FGG144
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL600V2-FGG144
Processor Series
AGL600
Core
IP Core
Maximum Operating Frequency
526.32 MHz, 892.86 MHz
Number Of Programmable I/os
97
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL600V2-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGL600V2-FGG144I
Manufacturer:
ACTEL
Quantity:
101
Company:
Part Number:
AGL600V2-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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IGLOO DC and Switching Characteristics
Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
2- 12
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P
3. P
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
5. Applicable for IGLOO V2 devices only.
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC7 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
5. Applicable for IGLOO V2 devices only.
3.3V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
3.3 V PCI
3.3 V PCI-X
3.3V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
1.2 V LVCMOS Wide Range
DC7
AC10
is the static power (where applicable) measured on VCCI.
is the total dynamic power measured on VCCI.
Applicable to Standard Plus I/O Banks
Applicable to Standard I/O Banks
5
5
4
4
5
5
C
C
LOAD
LOAD
10
10
5
5
5
5
5
5
5
5
5
5
5
5
5
5
(pF)
(pF)
R ev i sio n 1 8
VCCI (V)
VCCI (V)
1.2
1.2
1.2
1.2
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
2.5
1.8
1.5
Static Power
PDC7 (mW)
Static Power
PDC7 (mW)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
PAC10 (µW/MHz)
PAC10 (µW/MHz)
Dynamic Power
Dynamic Power
1
1
122.16
122.16
181.06
181.06
104.38
104.38
68.37
34.53
23.66
14.90
14.90
59.86
31.26
21.96
13.49
13.49
3
3
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