A3P600L-FGG484 Actel, A3P600L-FGG484 Datasheet - Page 127
A3P600L-FGG484
Manufacturer Part Number
A3P600L-FGG484
Description
FPGA - Field Programmable Gate Array 6K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P600L-FGG484
Processor Series
A3P600
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
235
Data Ram Size
110592
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P600L-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P600L-FGG484
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
A3P600L-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Figure 2-34 • Output DDR Timing Diagram
Table 2-192 • Output DDR Propagation Delays
Data_F
Data_R
CLK
CLR
Out
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDROCLKQ
DDRISUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDOMAX
For specific junction temperature and voltage supply levels, refer to
6
t
Timing Characteristics
DDROCLR2Q
Commercial-Case Conditions: T
1
1.5 V DC Core Voltage
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
t
DDROREMCLR
t
DDROREMCLR
7
2
t
t
DDROCLKQ
DDROHD1
7
t
DDROSUD2
J
= 70°C, Worst-Case VCC = 1.425 V
8
Description
3
2
R e v i s i o n 9
t
DDROHD2
8
Table 2-6 on page 2-7
4
9
3
ProASIC3L Low Power Flash FPGAs
t
DDRORECCLR
9
10
0.72
0.39
0.39
0.00
0.00
0.82
0.00
0.23
0.19
0.31
0.28
4
for derating values.
–1
5
0.84
0.45
0.45
0.00
0.00
0.96
0.00
0.27
0.22
0.36
0.32
Std.
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
2- 113
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