A3P600L-FGG484 Actel, A3P600L-FGG484 Datasheet - Page 125
A3P600L-FGG484
Manufacturer Part Number
A3P600L-FGG484
Description
FPGA - Field Programmable Gate Array 6K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P600L-FGG484
Processor Series
A3P600
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
235
Data Ram Size
110592
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P600L-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P600L-FGG484
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
A3P600L-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-190 • Input DDR Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD1
DDRISUD2
DDRIHD1
DDRIHD2
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
1.2 V DC Core Voltage
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (fall)
Data Setup for Input DDR (rise)
Data Hold for Input DDR (fall)
Data Hold for Input DDR (rise)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
J
Description
= 70°C, Worst-Case VCC = 1.14 V
R e v i s i o n 9
Table 2-6 on page 2-7
ProASIC3L Low Power Flash FPGAs
0.43
0.61
0.44
0.39
0.00
0.00
0.73
0.89
0.00
0.35
0.22
0.36
0.32
TBD
–1
for derating values.
0.37
0.52
0.38
0.33
0.00
0.00
0.62
0.76
0.00
0.30
0.19
0.31
0.28
TBD
Std.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 111
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