LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 328
LFXP2-8E-5FTN256I
Manufacturer Part Number
LFXP2-8E-5FTN256I
Description
FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256I
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
226304
Number Of I /o
201
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package
256FTBGA
Family Name
LatticeXP2
Device Logic Units
8000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
201
Ram Bits
226304
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5FTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Table 17-3. Procedure for Converting a JEDEC File to a Bitstream using the ispUFW (Continued)
Once the bitstream is generated, follow the procedures shown in Figure 17-2 and Table 17-4 to program the bit-
stream into the SPI Flash device on ispVM System. ispVM System supports quite many useful SPI Flash opera-
tions. Most operations are intuitively understood by users thus do not require detail description in this document.
After the SPI Flash is programmed with a valid bitstream, and if the LatticeXP2 device is not yet programmed,
using JTAG refresh or power cycling the LatticeXP2 device will activate the Master SPI port to boot from the SPI
Flash device. The PROGRAMN pin will work as long as the JTAG port has not been used. If the JTAG port has
been used, power cycle the LatticeXP2 device will re-enable the PROGRAMN pin. Please refer to Critical Point 2
above for more details.
The mechanical detail on the JTAG port in the LatticeXP2 device serving as a SPI host to access the external SPI
Flash devices can be found in the reference section at the end of this document.
Figure 17-2. Using ispVM to Program a Bitstream into the SPI Flash Device
Steps
5
6
This is optional. The default is 2.5 MHz. The maximum frequency recommended is 15 MHz due to the +/- 30%
variance of the clock oscillator of the LatticeXP2 devices and the typical slow read (opcode = 0x03) frequency is
20 MHz maximum of the SPI Flash devices.
The other settings following the Frequency shall be left to default to as shown. Just for completeness, the purpose
of the other settings are described below:
Ignore ID Code = Insert the LatticeXP2 device 32-bit Device ID checking into the bitstream. Default = do not check
IDCODE.
Program Secure = Insert the program security fuse command into the bitstream. Default = per the JEDEC file G
field setting.
Disable CRC Calculation = Remove CRC checking in the bitstream. OFF = the bitstream has CRC checking.
(Note: The LatticeXP2 devices use the CRC value to check against bitstream corruption for configuration pass/fail
decision. User must not change this setting when generating the final customer ready bitstream. These features
are provided to aid board development and debugging.)
Click the file generation button to generate the bitstream.
1
1 1
17-10
Description
9
9 9
3
3 3
2
2 2
10
10
8
8 8
4
4 4
LatticeXP2 Dual Boot Feature
5
5 5
6
6 6
7
7 7
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