LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 180

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-31. FIFO_DC without Output Registers, End of Data Write Cycle
In this case, the Almost Full flag is in the 2 location before the FIFO_DC is filled. The Almost Full flag is asserted
when the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO_DC.
Data_X data inputs do not get written as the FIFO_DC is full (the Full flag is high).
Note that the assertion of these flags is immediate and there is no latency when they go true.
Now let us look at the waveforms when the contents of the FIFO_DC are read out. Figure 10-32 shows the start of
the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown.
In this case, note that the de-assertion is delayed by two clock cycles.
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Data_N-2
Data_N-1
10-30
Invalid Q
Data_N
Data_X
LatticeXP2 Memory Usage Guide
Data_X