LFXP2-8E-5FTN256I Lattice, LFXP2-8E-5FTN256I Datasheet - Page 238

• Manufacturer Part Number: LFXP2-8E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256I

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 226304
• Number Of I /o: 201
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package: 256FTBGA
• Family Name: LatticeXP2
• Device Logic Units: 8000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 201
• Ram Bits: 226304
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11-41 shows the primitive symbol for the DELAYB mode.
Figure 11-41. DELAYB Symbol
Table 11-11 lists the port names and descriptions for the DELAYB primitive.
Table 11-11. DELAYB Port Names
Design Rules/Guidelines
Listed below are some rules and guidelines for implementing generic DDR interfaces in LatticeXP2 devices.
• When implementing a 2x gearing mode, the complement PIO registers are used. This complementary PIO regis-
DDR Usage In IPexpress
IPexpress can be used to configure and generate the DDR Memory Interface and Generic DDR Module. The tool
will generate an HDL module that will contain the DDR primitives. This module can be using in the top level design.
Figure 11-42 shows the main window of IPexpress. The DDR_Generic and DDR_MEM options under Architech-
ture->IO are used to configure the DDR modules.
ter can no longer be used and should not be connected.
2. Fixed – When choosing the fixed value, the user will also need to choose from one of the 16 multiplier val-
3. FIXED_XGMII – The DEL [3:0] will be configured with the delay value required when implementing a
ues. This will tie the inputs DEL[3:0] of the DELAYB block to a fixed value depending on the multiplier value
chosen.
XGMII interface.
A
DEL (0:3)
Z
Port Name
I/O
O
I
I
A
DEL(0:3)
DDR input from the sysIO buffer
Delay inputs
Delay DDR data
DELAYB
11-34
Definition
Z
LatticeXP2 High-Speed I/O Interface