A3PN030-ZVQG100 Actel, A3PN030-ZVQG100 Datasheet - Page 77
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A3PN030-ZVQG100
Manufacturer Part Number
A3PN030-ZVQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet
1.A3PN030-ZVQG100.pdf
(106 pages)
Specifications of A3PN030-ZVQG100
Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
77
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3PN030-ZVQG100
Manufacturer:
ACTEL
Quantity:
1 213
Company:
Part Number:
A3PN030-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3PN030-ZVQG100I
Manufacturer:
NXP
Quantity:
4 600
Company:
Part Number:
A3PN030-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-74 • RAM4K9
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
C2CWWL
C2CWWH
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Commercial-Case Conditions: T
Address Setup time
Address Hold time
REN_B, WEN_B Setup time
REN_B, WEN_B Hold time
BLK_B Setup time
BLK_B Hold time
Input data (DI) Setup time
Input data (DI) Hold time
Clock High to New Data Valid on DO (output retained, WMODE = 0)
Clock High to New Data Valid on DO (flow-through, WMODE = 1)
Clock High to New Data Valid on DO (pipelined)
Address collision clk-to-clk delay for reliable write after write on same
address; applicable to closing edge
Address collision clk-to-clk delay for reliable write after write on same
address; applicable to rising edge
Address collision clk-to-clk delay for reliable read access after write on same
address; applicable to opening edge
Address collision clk-to-clk delay for reliable write access after read on same
address; applicable to opening edge
RESET_B Low to Data Out Low on DO (flow through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B Removal
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle time
Maximum Frequency
Timing Characteristics
J
Description
= 70°C, Worst-Case VCC = 1.425 V
R e v i s i o n 8
0.25
0.00
0.14
0.10
0.23
0.02
0.18
0.00
1.79
2.36
0.89
0.33
0.30
0.45
0.49
0.92
0.92
0.29
1.50
0.21
3.23
310
–2
ProASIC3 nano Flash FPGAs
0.28
1.02
0.24
0.00
0.16
0.11
0.27
0.02
0.21
0.00
2.03
2.68
0.28
0.26
0.38
0.42
1.05
1.05
0.33
1.71
3.68
272
–1
0.33
0.00
0.19
0.13
0.31
0.02
0.25
0.00
2.39
3.15
1.20
0.25
0.23
0.34
0.37
1.23
1.23
0.38
2.01
0.29
4.32
Std. Units
231
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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