A3PN030-ZVQG100 Actel, A3PN030-ZVQG100 Datasheet - Page 60
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A3PN030-ZVQG100
Manufacturer Part Number
A3PN030-ZVQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet
1.A3PN030-ZVQG100.pdf
(106 pages)
Specifications of A3PN030-ZVQG100
Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
77
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3PN030-ZVQG100
Manufacturer:
ACTEL
Quantity:
1 213
Company:
Part Number:
A3PN030-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3PN030-ZVQG100I
Manufacturer:
NXP
Quantity:
4 600
Company:
Part Number:
A3PN030-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
ProASIC3 nano DC and Switching Characteristics
Figure 2-16 • Input DDR Timing Diagram
Table 2-62 • Input DDR Propagation Delays
2- 46
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage-supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (Fall)
Data Setup for Input DDR (Rise)
Data Hold for Input DDR (Fall)
Data Hold for Input DDR (Rise)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal time for Input DDR
Asynchronous Clear Recovery time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
t
t
1
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
t
Description
DDRICLKQ1
J
= 70°C, Worst Case VCC = 1.425 V
4
2
R e visio n 8
3
5
t
DDRICLKQ2
t
DDRISUD
Table 2-6 on page 2-5
6
4
5
350.00
0.27
0.39
0.28
0.25
0.00
0.00
0.46
0.57
0.00
0.22
0.22
0.36
0.32
–2
7
350.00
t
0.31
0.44
0.32
0.28
0.00
0.00
0.53
0.65
0.00
0.25
0.25
0.41
0.37
DDRIHD
–1
t
for derating values.
8
DDRIRECCLR
6
7
350.00
0.37
0.52
0.38
0.33
0.00
0.00
0.62
0.76
0.00
0.30
0.30
0.48
0.43
Std.
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns