A3PN030-ZVQG100 Actel, A3PN030-ZVQG100 Datasheet - Page 41
![FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano](/photos/16/14/161495/tqfp-100_sml.jpg)
A3PN030-ZVQG100
Manufacturer Part Number
A3PN030-ZVQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet
1.A3PN030-ZVQG100.pdf
(106 pages)
Specifications of A3PN030-ZVQG100
Processor Series
A3PN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
77
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3PN030-ZVQG100
Manufacturer:
ACTEL
Quantity:
1 213
Company:
Part Number:
A3PN030-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3PN030-ZVQG100I
Manufacturer:
NXP
Quantity:
4 600
Company:
Part Number:
A3PN030-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-35 • 3.3 V LVCMOS Wide Range High Slew
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
2. For specific junction temperature and voltage supply levels, refer to
3. Software default selection highlighted in gray.
equivalent software default drive strength. These values are for normal ranges only.
Commercial-Case Conditions: T
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Equivalent
Software
Strength
Option
Default
Drive
2 mA
4 mA
6 mA
8 mA
1
Speed
Grade
Std.
Std.
Std.
Std.
–1
–2
–1
–2
–1
–2
–1
–2
t
DOUT
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
10.83 0.04
10.83 0.04
9.22
8.09
9.22
8.09
6.78
5.77
5.06
6.78
5.77
5.06
t
J
DP
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
0.04
0.03
0.04
0.04
0.03
0.04
0.03
0.04
0.03
0.04
t
DIN
R e v i s i o n 8
1.57
1.33
1.17
1.57
1.33
1.17
1.57
1.33
1.17
1.57
1.33
1.17
t
PY
t
2.18
1.85
1.62
2.18
1.85
1.62
2.18
1.85
1.62
2.18
1.85
1.62
PYS
Table 2-6 on page 2-5
t
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
EOUT
10.83 9.48
10.83 9.48
9.22
8.09
9.22
8.09
6.78
5.77
5.06
6.78
5.77
5.06
t
ZL
8.06
7.08
8.06
7.08
5.72
4.87
4.27
5.72
4.87
4.27
t
for derating values.
ZH
ProASIC3 nano Flash FPGAs
3.25
2.77
2.43
3.25
2.77
2.43
3.72
3.16
2.78
3.72
3.16
2.78
t
LZ
3.56
3.03
2.66
3.56
3.03
2.66
4.35
3.70
3.25
4.35
3.70
3.25
t
HZ
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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