SST25VF080B-50-4C-QAF Microchip Technology, SST25VF080B-50-4C-QAF Datasheet - Page 11

• Manufacturer Part Number: SST25VF080B-50-4C-QAF
• Description: Flash 8M (1Mx8) 50MHz 2.7-3.6V Commercial
• Manufacturer: Microchip Technology

Specifications of SST25VF080B-50-4C-QAF

• Architecture: Sectored
• Interface Type: 4-Wire
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 4 KB x 256
• Memory Type: SPI Flash
• Memory Size: 8 Mbit
• Operating Temperature: + 70 C
• Package / Case: WSON
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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©2011 Silicon Storage Technology, Inc.
High-Speed-Read (66/80 MHz)
The High-Speed-Read instruction supporting up to 66 MHz (for SST25VF080B-50-xx-xxxx) or 80 MHz
(for SST25VF040B-80-xx-xxxx) Read is initiated by executing an 8-bit command, 0BH, followed by
address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-
Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-
fied address location. The data output stream is continuous through all addresses until terminated by a
low to high transition on CE#. The internal address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. Once the data from
address location FFFFFH has been read, the next output will be from address location 00000H.
Figure 6: High-Speed-Read Sequence
SCK
CE#
SO
SI
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
MODE 3
MODE 0
MSB
0 1 2 3 4 5 6 7 8
0B
HIGH IMPEDANCE
MSB
ADD.
15 16
11
ADD.
23 24
ADD.
IL
or V
31 32
IH
)
X
8 Mbit SPI Serial Flash
39 40
MSB
D
OUT
N
47 48
D
N+1
OUT
55 56
D
N+2
SST25VF080B
OUT
63 64
D
N+3
OUT
S71296-05-000
71 72
1296 HSRdSeq.0
Data Sheet
D
N+4
OUT
80
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