IRF9530SPBF Vishay, IRF9530SPBF Datasheet - Page 7

MOSFET Power P-Chan 100V 12 Amp

IRF9530SPBF

Manufacturer Part Number
IRF9530SPBF
Description
MOSFET Power P-Chan 100V 12 Amp
Manufacturer
Vishay
Type
Power MOSFETr
Datasheet

Specifications of IRF9530SPBF

Transistor Polarity
P-Channel
Minimum Operating Temperature
- 55 C
Configuration
Single
Resistance Drain-source Rds (on)
0.3 Ohm @ 10 V
Forward Transconductance Gfs (max / Min)
3.7 S
Drain-source Breakdown Voltage
100 V
Gate-source Breakdown Voltage
+/- 20 V
Continuous Drain Current
12 A
Power Dissipation
3700 mW
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Package / Case
SMD-220
Continuous Drain Current Id
-12A
Drain Source Voltage Vds
-100V
On Resistance Rds(on)
300mohm
Rds(on) Test Voltage Vgs
-10V
Leaded Process Compatible
Yes
Number Of Elements
1
Polarity
P
Channel Mode
Enhancement
Drain-source On-res
0.3Ohm
Drain-source On-volt
100V
Gate-source Voltage (max)
±20V
Drain Current (max)
12A
Output Power (max)
Not RequiredW
Frequency (max)
Not RequiredMHz
Noise Figure
Not RequireddB
Power Gain
Not RequireddB
Drain Efficiency
Not Required%
Operating Temp Range
-55C to 175C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
2 +Tab
Package Type
SMD-220
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91077.
Document Number: 91077
S10-1728-Rev. B, 02-Aug-10
Re-applied
voltage
Reverse
recovery
current
+
R
-
g
D.U.T.
• Compliment N-Channel of D.U.T. for driver
Note
a. V
Note
D.U.T. V
Driver gate drive
D.U.T. l
Inductor current
GS
= - 5 V for logic level and - 3 V drive devices
P.W.
SD
DS
waveform
waveform
Peak Diode Recovery dV/dt Test Circuit
Body diode forward drop
Ripple ≤ 5 %
Period
Body diode forward
+
-
Fig. 14 - For P-Channel
• dV/dt controlled by R
• I
• D.U.T. - device under test
current
SD
Diode recovery
controlled by duty factor “D”
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
dV/dt
current transformer
dI/dt
D =
-
g
Period
P.W.
+
I
V
SD
V
GS
IRF9530S, SiHF9530S
DD
= - 10 V
+
-
V
DD
a
Vishay Siliconix
www.vishay.com
7

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