ASD5020L640INT Arctic Silicon Devices, ASD5020L640INT Datasheet - Page 15

• Manufacturer Part Number: ASD5020L640INT
• Description: ADC (A/D Converters) Mul-Md 12bit/640MSPS 8-bit 1000 MSPS ADC
• Manufacturer: Arctic Silicon Devices

Specifications of ASD5020L640INT

• Number Of Converters: 1
• Number Of Adc Inputs: 2
• Conversion Rate: 640 MSPs
• Resolution: 12 bit
• Snr: 70 dB
• Voltage Reference: 1 V
• Supply Voltage (max): 2 V
• Supply Voltage (min): 1.7 V
• Maximum Power Dissipation: 490 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-48
• Input Voltage: 1.8 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preliminary Product Specification
Register Description
Software Reset
Setting the rst register bit to '1', restores the default value of all the internal registers including the rst register bit itself.
Modes of Operation
The ASD5020 has three main high speed operating modes controlled by the register bit high_speed_mode as defined in
table 6. Power down mode, as described in section 'Startup Initialization', must be activated after or during a change of
operating mode to ensure correct operation. The high speed modes all utilize interleaving to achieve high sampling
speed. Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, while single
channel mode interleave all 8 ADC branches.
Only one of the 3 bits should be activated at the same time.
clk_divide<1:0> allows the user to apply an input clock frequency higher than the sampling rate. The clock divider will
divide the input clock frequency by a factor of 1, 2, 4, or 8, defined by the clk_divide<1:0> register. By setting the
clk_divide<1:0> value relative to the channel_num<2:0> value, the same input clock frequency can be used for all
settings on number of channels. e.g: When increasing the number of channels from 1 to 4, the maximum sampling rate is
reduced by a factor of 4. By letting clk_divide<1:0> follow the channel_num<2:0> value, and change it from 1 to 4, the
internal clock divider will provide the reduction of the sampling rate without changing the input clock frequency.
ASD5020
rst
high_speed_mode
<2:0>
clk_divide<1:0>
Name
Name
high_speed_mode
0
0
1
<2:0>
0
1
0
Self-clearing software reset.
Enable high speed mode, Single,
Dual or Quad channel.
Define clock divider factor: 1, 2, 4 or 8
1
0
0
Dual channel 12-bit high speed
clk_divide<1:0>
Description
Description
Single channel 12-bit high
Quad channel 12-bit high
00 (default)
Mode of operation
01
10
11
speed mode
speed mode
mode
Table 7: Clock Divider Factor
Table 6: Modes of operation
High speed mode –
Quad Channel
Clock Divider Factor
rev 2.0, 2010.11.08
Divide by 1
Default
Default
Inactive
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channel2 to ADC2, channel3 to ADC3 and channel 4 to ADC4
Dual channel where channel 1 is made by interleaving ADC1
and ADC2, channel 2 by interleaving ADC3 and ADC4
Quad channel where channel 1 corresponds to ADC1,
1
2
4
8
Single channel by interleaving ADC1to ADC4
D15 D14D13D12D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14D13D12D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Description
Input clock frequency / 1
Input clock frequency / 2
Input clock frequency / 4
Input clock frequency / 8
Sampling rate (FS)
X X
0 X X X
High Speed Mode
X
Address
Address
0x00
Hex
Hex