WM8776SEFT/V Wolfson Microelectronics, WM8776SEFT/V Datasheet - Page 20

• Manufacturer Part Number: WM8776SEFT/V
• Description: Audio CODECs Stereo CODEC with 5-Ch Mux
• Manufacturer: Wolfson Microelectronics

Specifications of WM8776SEFT/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8776
w
AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital Audio
Interface. 5 popular interface formats are supported:
•
•
•
•
•
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
In left justified, right justified and I
input and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with
ADCLRC/DACLRC indicating whether the left or right channel is present. ADCLRC/DACLRC is also
used as a timing reference to indicate the beginning or end of the data words.
In left justified, right justified and I
period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word
length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on
ADCLRC/DACLRC is acceptable provided the above requirements are met.
In DSP modes A or B, DACLRC is used as a frame sync signal to identify the MSB of the first word.
The minimum number of DACBCLKs per DACLRC period is 2 times the selected word length. Any
mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The
ADC data may also be output in DSP modes A or B, with ADCLRC used as a frame sync to identify
the MSB of the first word. The minimum number of ADCBCLKs per ADCLRC period is 2 times the
selected word length.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN is sampled by the WM8776 on the first rising edge of
DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and
changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge
of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right
samples (Figure 13).
Figure 13 Left Justified Mode Timing Diagram
DACBCLK/
ADCBCLK
DACLRC/
ADCLRC
DOUT
DIN/
Left Justified mode
Right Justified mode
I
DSP mode A
DSP mode B
2
S mode
MSB
1
2
3
LEFT CHANNEL
2
2
S modes, the digital audio interface receives DAC data on the DIN
S modes; the minimum number of BCLKs per DACLRC/ADCLRC
n-2 n-1
n
LSB
MSB
1/fs
1
2
3
RIGHT CHANNEL
PD, Rev 4.1, September 2008
n-2 n-1
n
LSB
Production Data
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