KIT33912G5DGEVME Freescale Semiconductor, KIT33912G5DGEVME Datasheet - Page 89

• Manufacturer Part Number: KIT33912G5DGEVME
• Description: Power Management Modules & Development Tools 33912G5 LIN SBC KIT
• Manufacturer: Freescale Semiconductor
• Type: Motor / Motion Controllers & Driversr

Specifications of KIT33912G5DGEVME

• Interface Type: SPI
• Product: Power Management Modules
• Silicon Manufacturer: Freescale
• Silicon Core Number: MC33912
• Kit Application Type: Interface
• Application Sub Type: LIN System
• Kit Contents: Board, CD, Misc Cable
• Rohs Compliant: Yes
• For Use With/related Products: MC33912
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt Mask Register - IMR
sources. The respective flags within the Interrupt Source
Register (ISR) will continue to work but will not generate
interrupts to the MCU. The 5.0 V Regulator over-temperature
prewarning interrupt and Under-Voltage (VSUV) interrupts
can not be masked and will always cause an interrupt.
HSM - High Side Interrupt Mask
the high side block.
LSM - Low Side Interrupt Mask
the low side block.
Table 62. Interrupt Sources
Analog Integrated Circuit Device Data
Freescale Semiconductor
ISR3 ISR2 ISR1 ISR0
0
0
0
0
0
0
0
This register allows masking of some of the interrupt
Writing to the IMR will return the ISR.
This write-only bit enables/disables interrupts generated in
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = LS Interrupts Enabled
0 = LS Interrupts Disabled
Table 60. Interrupt Mask Register - $E
Condition
0
0
0
0
1
1
1
Reset
Reset
Value
Write
0
0
1
1
0
0
1
HSM
C3
1
0
1
0
1
0
1
0
(Low Voltage and VDD over-temperature)
LSM
C2
1
POR
Voltage Monitor Interrupt
LINM
C1
1
none maskable
no interrupt
VMM
-
-
-
C0
1
Interrupt Source
LINM - LIN Interrupts Mask
the LIN block.
VMM - Voltage Monitor Interrupt Mask
the Voltage Monitor block. The only maskable interrupt in the
Voltage Monitor Block is the V
Interrupt Source Register - ISR
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10 µs and
then be driven low again.
Mask Register (IMR).
ISRx - Interrupt Source Register
Table
sources are handled sequentially multiplex.
LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN
This write-only bit enables/disables interrupts generated in
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
This write-only bit enables/disables interrupts generated in
1 = Interrupts Enabled
0 = Interrupts Disabled
This register allows the MCU to determine the source of
This register is also returned when writing to the Interrupt
These read-only bits indicate the interrupt source following
In case more than one interrupt is pending, the interrupt
62. If no interrupt is pending then all bits are 0.
Table 61. Interrupt Source Register - $E/$F
HS Interrupt (Over-temperature)
LS Interrupt (Over-temperature)
Read
Lx Wake-up from Stop mode-
Voltage Monitor Interrupt
OC) or LIN Wake-up
Forced Wake-up
(High Voltage)
no interrupt
maskable
ISR3
S3
FUNCTIONAL DEVICE OPERATIONS
ISR2
S2
SUP
over-voltage interrupt.
ISR1
S1
ISR0
S0
Priority
highest
lowest
none
33912
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