KIT33912G5DGEVME Freescale Semiconductor, KIT33912G5DGEVME Datasheet - Page 76

• Manufacturer Part Number: KIT33912G5DGEVME
• Description: Power Management Modules & Development Tools 33912G5 LIN SBC KIT
• Manufacturer: Freescale Semiconductor
• Type: Motor / Motion Controllers & Driversr

Specifications of KIT33912G5DGEVME

• Interface Type: SPI
• Product: Power Management Modules
• Silicon Manufacturer: Freescale
• Silicon Core Number: MC33912
• Kit Application Type: Interface
• Application Sub Type: LIN System
• Kit Contents: Board, CD, Misc Cable
• Rohs Compliant: Yes
• For Use With/related Products: MC33912
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RST Wake-up
RST pin is held low long enough to pass the internal glitch
filter. Then, the 33912 will change to Normal Request or
Normal modes depending on the WDCONF pin
configuration. The RST wake-up does not generate an
interrupt and is not reported via SPI.
configured:
configured:
WINDOW WATCHDOG
which is active in Normal mode. The watchdog can be
configured by an external resistor connected to the WDCONF
pin. The resistor is used to achieve higher precision in the
timebase used for the watchdog.
MOD bits of the Mode Control Register (MCR).
not allowed, but after the first half of the SPI timeout window,
the clear operation opens. If a clear operation is performed
outside the window, the 33912 will reset the MCU, in the
same way as when the watchdog overflows.
76
33912
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
While in Stop mode, the 33912 can wake-up when the
From Stop mode, the following wake-up events can be
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• CS wake-up
• LIN wake-up
• RST wake-up
From Sleep mode, the following wake-up events can be
• Wake-up from Lx inputs without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
• LIN wake-up
The 33912 includes a configurable window watchdog
SPI clears are performed by writing through the SPI in the
During the first half of the SPI timeout, watchdog clears are
WD TIMING X 50%
NO WATCHDOG CLEAR
Figure 39. Window Watchdog Operation
WINDOW CLOSED
WD TIMING SELECTED BY REGISTER
ALLOWED
ON WDCONF PIN
WD PERIOD (t
PWD
WD TIMING X 50%
FOR WATCHDOG
WINDOW OPEN
)
CLEAR
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request mode. The WDOFF bit
in the Watchdog Status Register (WDSR) will be set. This
condition is only detected during Reset mode.
the watchdog falls back to the internal lower precision
timebase of 150 ms (typ.) and signals the faulty condition
through the Watchdog Status Register (WDSR).
prescaler which can be configured by the Timing Control
Register (TIMCR). During Normal Request mode, the
window watchdog is not active but there is a 150 ms (typ.)
timeout for leaving the Normal Request mode. In case of a
timeout, the 33912 will enter into Reset mode, resetting the
microcontroller before entering again into Normal Request
mode.
HIGH SIDE OUTPUT PINS HS1 AND HS2
small resistive loads or LEDs incorporating the following
features:
the High Side Control Register (HSCR).
PWM Capability (direct access)
direct control via the PWMIN pin.
Control Register (HSCR), then the HS1 driver is turned on if
the PWMIN pin is high and turned of if the PWMIN pin is low.
This applies to HS2 configuring HS2 and PWMHS2 bits.
To disable the watchdog function in Normal mode the user
If neither a resistor nor a connection to ground is detected,
The watchdog timebase can be further divided by a
These outputs are two high side drivers intended to drive
• PWM capability (software maskable)
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• High-voltage shutdown (software maskable)
• Cyclic sense
The high side switches are controlled by the bits HS1:2 in
Each high side driver offers additional (to the SPI control)
If both the bits HS1 and PWMHS1 are set in the High Side
Analog Integrated Circuit Device Data
Freescale Semiconductor