CP2110-F01-GM Silicon Laboratories Inc, CP2110-F01-GM Datasheet - Page 20

IC HID USB-TO-UART BRIDGE 24QFN

CP2110-F01-GM

Manufacturer Part Number
CP2110-F01-GM
Description
IC HID USB-TO-UART BRIDGE 24QFN
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of CP2110-F01-GM

Package / Case
24-WFQFN Exposed Pad
Applications
UART-to-USB Bridge
Interface
UART, USB
Voltage - Supply
1.8V, 3 V ~ 3.6 V
Mounting Type
Surface Mount
Input Voltage Range (max)
3.6 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current (max)
18.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-2003 - KIT EVAL FOR CP2110
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-2006-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CP2110-F01-GM
Manufacturer:
ST
Quantity:
12 000
Part Number:
CP2110-F01-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
CP2110
Alternatively, if 3.0 to 3.6 V power is supplied to the V
device with the voltage regulator bypassed. For this configuration, tie the REGIN input to V
regulator. A typical connection diagram showing the device in a self-powered application with the regulator
bypassed is shown in Figure 9.
The USB max power and power attributes descriptor must match the device power usage and configuration. See
application note “AN144: CP21xx Customization Guide” for information on how to customize USB descriptors for
the CP2110.
20
Connector
Note 1 : VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface
Note 2 : Avalanche transient voltage suppression diodes compatible with Full-speed USB should be
Note 3 : An external pull-up is not required, but can be added for noise immunity.
Note 4 : If programming the configuration ROM via USB, add a 4.7 F capacitor between VPP
USB
VBUS
Power
GND
3.3 V
D+
D-
voltage.
added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.
circuitry, and ensure that VDD is at least 3.3 V.
and ground. During a programming operation, do not connect the VPP pin to other
Figure 9. Typical Self-Powered Connection Diagram (Regulator Bypass)
1-5 F
Note 2
Note 1
0.1 F
VIO
VDD
REGIN
GND
VBUS
D+
D-
Rev. 1.0
DD
pin, the CP2110 can function as a USB self-powered
CP2110
GPIO.3_RS485
GPIO.1_RTS
GPIO.2_CTS
GPIO.5_RXT
GPIO.0_CLK
GPIO.4_TXT
SUSPEND
SUSPEND
GPIO.7
GPIO.8
GPIO.9
GPIO.6
RST
VPP
RX
TX
DD
to bypass the voltage
VIO
and GPIO
Suspend
Standard
Signals
Signals
4.7 F
UART
Note 3
4.7 k
Note 4

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