DS90UB902QSQE/NOPB National Semiconductor, DS90UB902QSQE/NOPB Datasheet - Page 31

• Manufacturer Part Number: DS90UB902QSQE/NOPB
• Description: IC SER/DESER 10-43MHZ 16B 40-LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB902QSQE/NOPB

• Function: Deserializer
• Data Rate: 688Mbps
• Input Type: CML
• Output Type: LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS90UB902QSQE/NOPBTR

DISPLAY MODE OPERATION
In Display mode, I
attached to the Serializer. The I
will detect if a transaction targets (local) registers within the
Serialier or the (remote) registers within the Deserializer or a
remote slave connected to the I
serializer. Commands are sent over the forward channel link
to initiate the transactions. The Deserializer will receive the
command and generate an I
bus. At the same time, the Deserializer will capture the re-
sponse on the I
on the bidirectional control channel. The Serializer parses the
response and passes the appropriate response to the Serial-
izer I
The physical device ID of the I
determined by the analog voltage on the ID[x] input. It can be
reprogrammed by using the DEVICE_ID register and setting
the bit . The device ID of the logical I
alizer is determined by programming the DES ID in the Seri-
alizer. The state of the ID[x] input on the Deserializer is used
to set the device ID. The I
will be bridged between the host controller to the remote
slave.
To configure the devices for display mode operation, set the
Serializer MODE pin to High and the Deserializer MODE pin
to Low. Before initiating any I
needs to be programmed with the target slave device address
and Serializer device address. DES_DEV_ID Register 0x06h
sets the Deserializer device address and SLAVE_DEV_ID
register 0x7h sets the remote target slave address. If the I
slave address matches any of registers values, the I
will hold the transaction allowing read or write to target device.
Note: In Display mode operation, registers 0x08h~0x17h on
Deserializer must be reset to 0x00.
CRC (CYCLIC REDUNDANCY CHECK) DETECTION
A 4-bit CRC per symbol is reserved for checking the link in-
tegrity during transmission. The reporting status pin (PASS)
is provided on the Deserializer side, which flags any mismatch
of data transmitted to and from the remote device. The
Deserializer's PLL must first be locked (LOCK pin HIGH) to
ensure the PASS status is valid. This error detection handling
generates an interrupt signal onto the PASS output pin; noti-
fying the host controller as soon as any errors are identified.
When an error occurs, the PASS asserts LOW. CRC registers
(CRC ERROR B0/B1) are also available for managing the
data error count.
The DS90UB901Q/902Q chipset provides several mecha-
nisms (operations) for ensuring data integrity in long distance
transmission and reception. The data error detection function
offers user flexibility and usability of performing bit-by-bit and
2
C bus.
2
C bus and return the response as a command
2
C transactions originate from the controller
2
C transactions between Ser/Des
2
C transaction on its local I
2
2
2
C commands, the Serializer
C slave core in the Serializer
C master interface of the De-
2
C slave in the Serializer is
2
C slave in the Deseri-
2
C slave
2
2
C
C
31
data transmission error checking. The error detection oper-
ating modes support data validation of the following signals:
•
•
•
PROGRAMMABLE CONTROLLER
An integrated I
DS90UB901Q Serializer and DS90UB902Q Deserializer. It
must be used to access and program the extra features em-
bedded within the configuration registers. Refer to
and
MULTIPLE DEVICE ADDRESSING
Some applications require multiple camera devices with the
same fixed address to be accessed on the same I
DS90UB901/902 provides slave ID matching/aliasing to gen-
erate different target slave addresses when connecting more
than two identical devices together on the same bus. This al-
lows the slave devices to be independently addressed. Each
device connected to the bus is addressable through a unique
ID by programming of the SLAVE_ID_MATCH register on
Deserializer. This will remap the SLAVE_ID_MATCH address
to the target SLAVE_ID_INDEX address; up to 8 ID indexes
are supported. The ECU Controller must keep track of the list
of I
vice. In a camera application, the microcontroller is located
on the Deserializer side. In this case, the microcontroller pro-
grams the slave address matching registers and handles all
data transfers to and from all slave I
in the event where camera modules are removed or replaced.
For example in the configuration shown in
•
•
•
•
If master controller transmits I
dress 0xC0 will forward the transaction to remote Camera A.
If the controller transmits slave address 0xA4, the DES B
0xC2 will recognize that 0xA4 is mapped to 0xA0 and will be
transmitted to the remote Camera B. If controller sends com-
mand to address 0xA6, the DES B 0xC2 will forward trans-
action to slave device 0xA2.
The Slave ID index/match is supported only in the camera
mode (SER: MODE pin = L; DES: MODE pin = H). For Multiple
device addressing in display mode (SER: MODE pin = H;
DES: MODE pin = L), use the I
Bidirectional Channel Control
Control VSYNC and HSYNC signals across serial link
Parallel video/pixel data across serial link
2
ECU is the I
The I
interfaces
The I
DES B to SER B
The I
interfaces
C peripherals in order to properly address the target de-
Table 2
2
2
2
C protocol is bridged from DES A to SER A and from
C interfaces in DES A and DES B are both slave
C interfaces in SER A and SER B are both master
for details of control registers.
2
2
C slave controller is embedded in each of the
C master and has an I
2
2
C slave 0xA0, the DES A ad-
C pass through function.
2
C devices. This is useful
2
C master interface
Figure
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2
C bus. The
28:
Table 1