DS90UB902QSQE/NOPB National Semiconductor, DS90UB902QSQE/NOPB Datasheet
DS90UB902QSQE/NOPB
Specifications of DS90UB902QSQE/NOPB
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DS90UB902QSQE/NOPB Summary of contents
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... Features ■ 10 MHz to 43 MHz input PCLK support ■ 160 Mbps to 688 Mbps data throughput Typical Application Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS90UB901Q/DS90UB902Q ■ Single differential pair interconnect ■ Bidirectional control interface channel with I ■ ...
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Block Diagrams www.national.com FIGURE 2. Block Diagram FIGURE 3. Application Block Diagram 2 30113528 30113529 ...
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Ordering Information NSID Package Description DS90UB901QSQE 32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch DS90UB901QSQ 32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm pitch DS90UB901QSQX 32–pin LLP, 5.0 X 5.0 X 0.8 mm, 0.5 mm ...
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DS90UB901Q Serializer Pin Descriptions Pin Name Pin No. I/O, Type LVCMOS PARALLEL INTERFACE DIN[13:0] 32, 31, 30, 29, Inputs, LVCMOS 27, 26, 24, 23, w/ pull down 22, 21, 20, 19, 18, 17 HSYNC 1 Inputs, LVCMOS w/ pull down ...
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Pin Name Pin No. I/O, Type Power, Digital VDDIO 25 Ground, DAP VSS DAP DS90UB902Q Pin Diagram Power for I/O stage. The single-ended inputs and SDA, SCL are powered from can be connected to a 1.8V ±5% ...
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DS90UB902Q Deserializer Pin Descriptions Pin Name Pin No. I/O, Type LVCMOS PARALLEL INTERFACE ROUT[13:0] 9, 10, 11, 12, Outputs, 14, 15, 17, 18, LVCMOS 19, 20, 21, 22, 23, 24 HSYNC 7 LVCMOS VSYNC 6 LVCMOS PCLK 5 LVCMOS GENERAL ...
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Pin Name Pin No. I/O, Type Output, PASS 31 LVCOMS FPD-LINK III INTERFACE Input/Output, RIN+ 35 Input/Output, RIN- 36 POWER AND GROUND VDDSSCG 4 Power, Digital VDDIO1/2/3 25, 16, 8 Power, Digital VDDD 13 Power, Digital VDDR 30 Power, Analog ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS Input Voltage I/O Voltage −0. (VDDIO + 0.3V) CML Driver I/O Voltage (V ...
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Symbol Parameter V High Level Output Voltage OH V Low Level Output Voltage OL I Output Short Circuit Current OS I TRI-STATE® Output Current PDB = 0V, OZ CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT Output Differential Voltage OD ...
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Symbol Parameter I Deserializer (Rx) VDDn DDR Supply Current (includes load current) I Deserializer (Rx) VDDIO DDIOR Supply Current (includes load current) I Deserializer (Rx) Supply DDRZ Current Power-down I DDIORZ Recommended Serializer Timing for PCLK Over recommended operating supply ...
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Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t CML Low-to-High LHT Transition Time t CML High-to-Low HLT Transition Time t Data Input Setup to PCLK DIS t Data Input Hold from PCLK ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Receiver Output Clock Period RCP t PCLK Duty Cycle PDC LVCMOS Low-to-High Transition t CLH Time t LVCMOS High-to-Low Transition CHL Time LVCMOS Low-to-High ...
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Bidirectional Control Bus AC Timing Specifications (SCL, SDA Compliant (Figure 4) Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter RECOMMENDED INPUT TIMING REQUIREMENTS f SCL Clock Frequency SCL t SCL Low Period LOW t SCL ...
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Bidirectional Control Bus DC Characteristics (SCL, SDA Over recommended supply and temperature ranges unless otherwise specified. Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis HY I TRI-STATE Output Current PDB ...
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AC Timing Diagrams and Test Circuits FIGURE 6. Serializer CML Output Load and Transition Times FIGURE 5. “Worst Case” Test Pattern 15 30113552 30113546 30113547 www.national.com ...
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FIGURE 7. Serializer VOD DC Diagram FIGURE 8. Differential VTH/VTL Definition Diagram FIGURE 9. Serializer Input Clock Transition Times 16 30113548 30113530 30113516 30113534 ...
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FIGURE 10. Serializer Setup/Hold Times FIGURE 11. Serializer Data Lock Time FIGURE 12. Serializer Delay FIGURE 13. Deserializer Data Lock Time 17 30113549 30113532 30113550 30113513 www.national.com ...
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FIGURE 14. Deserializer LVCMOS Output Load and Transition Times www.national.com FIGURE 15. Deserializer Delay FIGURE 16. Deserializer Output Setup/Hold Times FIGURE 17. Receiver Input Jitter Tolerance 18 30113514 30113511 30113531 30113558 ...
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FIGURE 18. Typical Serializer Jitter Transfer Function Curve at 43 MHz FIGURE 19. Typical Deserializer Input Jitter Tolerance Curve at 43 MHz FIGURE 20. Spread Spectrum Clock Output Profile 19 30113562 30113559 30113535 www.national.com ...
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TABLE 1. DS90UB901Q Control Registers Addr Name Bits Field (Hex) 7:1 DEVICE Device SER ID SEL 7:3 RESERVED 2 STANDBY 1 Reset DIGITAL 1 RESET0 0 DIGITAL RESET1 2 Reserved 7:0 RESERVED RX ...
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Addr Name Bits Field (Hex Bus Rate 7 BUS RATE 7:1 DES DEV ID 6 DES ID 0 RESERVED 7:1 SLAVE DEV ID 7 Slave ID 0 RESERVED 8 Reserved 7:0 RESERVED 9 ...
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Addr Name Bits Field (Hex) 7:4 RESERVED 3:2 RESERVED 12 GPIO[5] Config 1 GPIO5 DIR 0 GPIO5 EN GPCR[7] GPCR[6] GPCR[5] GPCR[4] General Purpose 13 7:0 Control Reg GPCR[3] GPCR[2] GPCR[1] GPCR[0] www.national.com R/W Default Description 0000'b Reserved 00'b Reserved ...
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TABLE 2. DS90UB902Q Control Registers Addr Name Bits (Hex) 7:1 DEVICE Device DES ID SEL 7:3 RESERVED 2 REM_WAKEUP 1 Reset 1 DIGITALRESET0 0 DIGITALRESET1 RESERVED 7:6 RESERVED Auto Clock 5 AUTO_CLOCK OSS ...
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Addr Name Bits (Hex) TX CRC 7 CHECKER ENABLE CRC Fault Tolerant Transmission RX CRC GEN 6 ENABLE VDDIO VDDIO Control 5 CONTROL 3 VDDIO Mode 4 VDDIO MODE Pass-Through 3 THROUGH Auto ACK 2 ...
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Addr Name Bits (Hex) RESERVED 7 RESERVED SCL Prescale 6:4 SCL_PRESCALE REM_NACK_TIM 6 Remote NACK 3 ER Remote NACK 2:0 NACK_TIMEOUT 7:1 SER DEV ID 7 SER ID 0 RESERVED 7:1 ID[0] INDEX 8 ID[0] Index 0 RESERVED 7:1 ID[1] ...
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Addr Name Bits (Hex) 7:1 ID[4] MATCH 14 ID[4] Match 0 RESERVED 7:1 ID[5] MATCH 15 ID[5] Match 0 RESERVED 7:1 ID[6] MATCH 16 ID[6] Match 0 RESERVED 7:1 ID[7] MATCH 17 ID[7] Match 0 RESERVED 18 RESERVED 7:0 RESERVED ...
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Addr Name Bits (Hex) 7:3 RESERVED 2 GPIO4 SET 21 GPIO[4] Config 1 GPIO4 DIR 0 GPIO4 EN 7:3 RESERVED 2 GPIO5 SET 22 GPIO[5] Config 1 GPIO5 DIR 0 GPIO5 EN GPCR[7] GPCR[6] GPCR[5] General Purpose GPCR[4] 23 7:0 ...
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Functional Description The DS90UB901Q/902Q FPD-Link III chipset is intended for camera applications. The Serializer/ Deserializer chipset op- erates from a 10 MHz to 43 MHz pixel clock frequency. The DS90UB901Q transforms a 16-bit wide parallel LVCMOS da- ta bus along ...
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SLAVE CLOCK STRETCHING In order to communicate and synchronize with remote de- vices on the bus through the bidirectional control channel, slave clock stretching must be supported by the I controller/MCU. The chipset utilizes bus clock stretching ...
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TABLE 3. ID[x] Resistor Value – DS90UB901Q ID[x] Resistor Value - DS90UB901Q Ser Resistor Address 7'b RID Ω (Note 11) (±0.1%) 0 7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0) GND 2.0k 7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2) ...
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DISPLAY MODE OPERATION In Display mode transactions originate from the controller attached to the Serializer. The slave core in the Serializer will detect if a transaction targets (local) registers within the Serialier or the ...
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PASS THROUGH I C pass-through provides an alternative means to indepen- 2 dently address slave devices. The mode enables or disables bidirectional control channel communication to the remote bus. This option ...
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SYNCHRONIZING MULTIPLE CAMERAS For applications requiring multiple cameras for frame-syn- chronization recommended to utilize the General Pur- pose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To synchronize the cameras properly, the system controller ...
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GENERAL PURPOSE I/O (GPIO) The DS90UB901Q/902Q has GPIO (2 dedicated and 4 programmable). GPIO[0] and GPIO[1] are always available and GPIO[2:5] are available depending on the parallel data bus size. DIN/ROUT[0:3] can be programmed into GPIOs (GPIO[2:5]) ...
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Note: AT-SPEED BIST is only available in the Camera mode and not the Display mode FIGURE 32. AT-SPEED BIST System Flow Diagram Step 1: Place the Deserializer in BIST Mode. Serializer and Deserializer power supply must be supplied. Enable the ...
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Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail. To end BIST, the system must pull BISTEN pin of the Dese- rializer LOW. The BIST duration is fully defined by the BIS- ...
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The chipset needs to be configured in Camera mode: Serializer MODE = 0 and Deserializer MODE = 1 • Serializer expects remote wake-up by default at power on. • Configure the control channel driver of the Deserializer to be ...
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Applications Information AC COUPLING The SER/DES supports only AC-coupled interconnects through an integrated DC balanced decoding scheme. Exter- For high-speed FPD-Link III transmissions, the smallest avail- able package should be used for the AC coupling capacitor. This will help minimize ...
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Figure 38 shows a typical connection of the DS90UB902Q Deserializer. FIGURE 38. DS90UB902Q Typical Connection Diagram — Pin Control 39 30113556 www.national.com ...
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TRANSMISSION MEDIA The Ser/Des chipset is intended to be used over a wide variety of balanced cables depending on distance and signal quality requirements. The Ser/Des employ internal termination pro- viding a clean signaling environment. The interconnect for FPD-Link III ...
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INTERCONNECT GUIDELINES See AN-1108 and AN-905 for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – space between the pair – space between pairs – space to ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted DS90UB901Q Serializer NS Package Number SQA32A DS90UB902Q Deserializer NS Package Number SQA40A 42 ...
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Notes 43 www.national.com ...
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