DS92LX1621SQX/NOPB National Semiconductor, DS92LX1621SQX/NOPB Datasheet - Page 30

• Manufacturer Part Number: DS92LX1621SQX/NOPB
• Description: IC SERIALIZER 10-50MHZ 32LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX1621SQX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
bus. At the same time, the Deserializer will capture the re-
sponse on the I
on the bi-directional control channel. The Serializer parses
the response and passes the appropriate response to the Se-
rializer I
The physical device ID of the I
determined by the analog voltage on the ID[x] input. It can be
reprogrammed by using the DEVICE_ID register and setting
the bit . The device ID of the logical I2C slave in the Deseri-
alizer is determined by programming the DES ID in the Seri-
alizer. The state of the CAD] input on the Deserializer is used
to set the device ID. The I
will be bridged between the host controller to the remote
slave.
To configure the devices for display mode operation, set the
Serializer M/S pin to HIGH and the Deserializer M/S pin to
LOW. Before initiating any I
needs to be programmed with the target slave device address
and Serializer device address. DES_DEV_ID Register 0x06h
sets the Deserializer device address and SLAVE_DEV_ID
register 0x7h sets the remote target slave address. If the I
slave address matches any of registers values, the I
will hold the transaction allowing read or write to target device.
Note: In Display mode operation, registers 0x08h~0x17h on
Deserializer must be reset to 0x00.
CRC (CYCLIC REDUNDANCY CHECK)
A 4-bit CRC per symbol is reserved for checking the link in-
tegrity during transmission. The reporting status pin (PASS)
is provided on the Deserializer side, which flags any mismatch
of data transmitted to and from the remote device. The
Deserializer's PLL must first be locked (LOCK pin is HIGH) to
ensure the PASS status is valid. This error detection handling
generates an interrupt signal onto the PASS output pin; noti-
fying the host controller as soon as any errors are identified.
When an error occurs, the PASS will asserts LOW. An ad-
justable interrupt threshold register is also available for man-
aging the data flow.
ERROR DETECTION
The DS92LX1621 / DS92LX1622 chipset provides several
error detection operations for ensuring data integrity in long
distance transmission and reception. The data error detection
function offers user flexibility and usability of performing bit-
by-bit and data transmission error checking. The error detec-
tion operating modes support data validation of the following
signals:
•
Bi-directional Control Channel control data detection
across serial link
2
C bus.
2
C bus and return the response as a command
2
C transactions between Ser/Des
2
C commands, the Serializer
2
C slave in the Serializer is
2
C slave
2
C
30
•
•
PROGRAMMABLE CONTROLLER
An integrated I
DS92LX1621 Serializer and DS92LX1622 Deserializer. It
must be used to access and program the extra features em-
bedded within the configuration registers. Refer to
and
MULTIPLE DEVICE ADDRESSING
Some applications require multiple camera devices with the
same fixed address to be accessed on the same I
DS92LX1621 / DS92LX1622 provide slave ID matching/alias-
ing to generate different target slave addresses when con-
necting more than two identical devices together on the same
bus. This allows the slave devices to be independently ad-
dressed. Each device connected to the bus is addressable
through
SLAVE_ID_MATCH register on Deserializer. This will remap
the SLAVE_ID_MATCH address to the target SLAVE_ID_IN-
DEX address; up to 8 ID indexes are supported. The host
controller must keep track of the list of I
to properly address the target device. In a camera application,
the microcontroller is located on the Deserializer side. In this
case, the microcontroller programs the slave address match-
ing registers and handles all data transfers to and from all
slave I
modules are removed or replaced. For example in the con-
figuration shown in
•
•
•
If the master controller transmits I
address 0xE0 will forward the transaction to remote Camera
A. If the controller transmits slave address 0xA2, the DES B
0xE2 will recognize that 0xA2 is mapped to 0xA0 and will be
transmitted to the remote Camera B. If controller sends com-
mand to address 0xB2, the DES B 0xE2 will forward trans-
action to slave device 0xB0.
The Slave ID index/match is supported only in the camera
mode (SER: M/S pin = L; DES: M/S pin = H). For Multiple
device addressing in display mode (SER: M/S pin = H; DES:
M/S pin = L), use the I
Control VSYNC and HSYNC signals across serial link
Parallel video/pixel data across serial link
Host device (FPGA, frame grabber, etc.) is the I
and has an I
The I
DES B to SER B
The I
interfaces
Table 2
2
C devices. This is useful in the event where camera
2
2
C protocol is bridged from DES A to SER A and from
C interfaces in SER A and SER B are both master
a
for details of control registers.
2
unique
C slave controller is embedded in each of the
2
C master interface
Figure
2
C pass through function.
ID
26:
by
2
C slave 0xA0, the DES A
programming
2
C peripherals in order
2
C bus. The
2
C master
of
Table 1
the