KSZ8873MLLI Micrel Inc, KSZ8873MLLI Datasheet - Page 58

• Manufacturer Part Number: KSZ8873MLLI
• Description: IC ETHERNET SWITCH 3PORT 64LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873MLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Micrel, Inc.
Note: Bits [2:0] are used for spanning tree support.
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
Associated with the ingress untagged packets, and used for egress tagging.
Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
September 2009
Bit
3
2
1
0
Bit
7-0
Bit
7-0
Bit
7
6
5
Pressure
Enable
Transmit
Enable
Receive
Enable
Learning
Disable
[15:8]
[7:0]
Port 3 MII
mode
Selection
Self-address
filtering
enable
MACA1
(not for
0x35)
Self-address
Name
Back
Name
Default Tag
Name
Default Tag
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
=1, Enable port’s half duplex back pressure
=0, Disable port’s half duplex back pressure
=1, Enable packet transmission on the port
=0, Disable packet transmission on the port
=1, Enable packet reception on the port
=0, Disable packet reception on the port
=1, Disable switch address learning capability
=0, Enable switch address learning
Description
Port’s default tag, containing
Description
Port’s default tag, containing
Description
=1, Port 3 MII MAC mode
=0, Port 3 MII PHY mode
Note: when port 3 is in MAC mode, this bit is used to enable
SMTXER3 pin.
=1, Enable port 1 self-address filtering MACA1
=0, Disable
=1, Enable port 2 Self-address filtering MACA2
7-5 : User priority bits
3-0 : VID[11:8]
7-0 : VID[7:0]
4 : CFI bit
58
Default
Inversion of
power
strapped
value of
SMRXDV3.
0
0
KSZ8873MLL/FLL/RLL
Default
0
1
1
0
Default
0x00
Default
0x01
M9999-092309-1.2