KSZ8873MLLI Micrel Inc, KSZ8873MLLI Datasheet - Page 53

• Manufacturer Part Number: KSZ8873MLLI
• Description: IC ETHERNET SWITCH 3PORT 64LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8873MLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Micrel, Inc.
Register 6 (0x06): Global Control 4
Register 7 (0x07): Global Control 5
Note:
September 2009
Bit
7
6
5
4
3
2-0
Bit
7-0
(1)
100BT Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63
Reserved
Switch MII Half
Duplex Mode
Switch MII
Flow Control
Enable
Switch MII
10BT
Null VID
Replacement
Broadcast
Storm
Protection
Rate
Bit [10:8]
Broadcast
Storm
Protection
Rate
Bit [7:0]
Name
Name
(1)
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Do not change the default values.
=1, Enable MII interface half-duplex mode.
=0, Enable MII interface full-duplex mode.
=1, Enable full duplex flow control on Switch MII interface.
=0, Disable full duplex flow control on Switch MII interface.
=1, The switch interface is in 10Mbps mode
=0, The switch interface is in 100Mbps mode
=1, Will replace NULL VID with port VID (12 bits)
=0, No replacement for NULL VID
This register along with the next register determines how many “64
byte blocks” of packet data are allowed on an input port in a preset
period. The period is 67ms for 100BT or 500ms for 10BT. The
default is 1%.
Description
This register along with the previous register determines how many
“64 byte blocks” of packet data are allowed on an input port in a
preset period. The period is 67ms for 100BT or 500ms for 10BT.
The default is 1%.
53
KSZ8873MLL/FLL/RLL
Default
0
Pin P1LED0 strap
option.
Pull-up(1): Half -duplex
mode
Pull-down(0): Full-
duplex mode
Note: P1LED0 has
internal pull-up.
Pin P1LED1 strap
option.
Pull- up(1): Enable
flow control
Pull-down(0): Disable
flow control
Note: P1LED1 has
internal pull-up.
Pin P3SPD strap
option.
Pull-up(1): Enable
10Mbps
Pull-down(0): Enable
100Mbps
Note: P3SPD has
internal pull-up.
0
000
Default
0x63
M9999-092309-1.2