WFIXF1110CC.B3-998845 Cortina Systems Inc, WFIXF1110CC.B3-998845 Datasheet - Page 20

• Manufacturer Part Number: WFIXF1110CC.B3-998845
• Description: IC ETHERNET MAC 10-PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of WFIXF1110CC.B3-998845

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1008-1037

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 1
Cortina Systems
SPI4-2 Interface Signal Descriptions (Sheet 1 of 2)
®
TDAT15_P, TDAT15_N
TDAT14_P, TDAT14_N
TDAT13_P, TDAT13_N
TDAT12_P, TDAT12_N
TDAT11_P, TDAT11_N
TDAT10_P, TDAT10_N
TDAT9_P, TDAT9_N
TDAT8_P, TDAT8_N
TDAT7_P, TDAT7_N
TDAT6_P, TDAT6_N
TDAT5_P, TDAT5_N
TDAT4_P, TDAT4_N
TDAT3_P, TDAT3_N
TDAT2_P, TDAT2_N
TDAT1_P, TDAT1_N
TDAT0_P, TDAT0_N
TDCLK_P
TDCLK_N
TCTL_P
TCTL_N
TSCLK
TSTAT1
TSTAT0
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Signal Name
G11
C9
J9
H7
E8
E9
B7
L5
C7
L8
G5
F7
G9
B5
H3
J6
D3
E4
M10
N10
C11
E6
E5
Ball Designator
H11
D9
K10
J8
E7
F9
C8
M5
C6
L7
H5
G6
H9
C5
J3
J5
Input
Input
Input
Output
Output
Type
LVDS
LVDS
LVDS
2.5 V
LVTTL
2.5 V
LVTTL
Standard
Transmit Data Bus: Carries
payload data and in-band control
words to the IXF1110 MAC
link-layer device.
Internally terminated differentially
with 100 Ω.
Transmit Data Clock: Clock
associated with TDAT[15:0] and
TCTL. Data and control lines are
driven off the rising and falling
edges of the clock.
Internally terminated differentially
with 100 Ω.
NOTE: If TDCLK is applied to the
IXF1110 MAC after the device has
come out of reset, the system
designer must ensure the TDCLK is
stable when applied. Failure to due
so can result in the IXF1110 MAC
training on a non-stable clock,
causing DIP4 errors and data
corruption.
Transmit Control: TCTL is High
when a control word is present on
TDAT[15:0]. Otherwise, TCTL is
Low.
Internally terminated differentially
with 100 Ω.
Transmit Status Clock: Clock
associated with TSTAT [1:0].
Frequency is equal to one-quarter
TDCLK.
Transmit FIFO Status: Carries
round-robin FIFO status
information, along with associated
error detection and framing.
4.2 Interface Signal Groups
Signal Description
Page 20