WFIXF1110CC.B3-998845 Cortina Systems Inc, WFIXF1110CC.B3-998845 Datasheet - Page 158
![no-image](/images/manufacturer_photos/0/1/162/cortina_systems_inc_sml.jpg)
WFIXF1110CC.B3-998845
Manufacturer Part Number
WFIXF1110CC.B3-998845
Description
IC ETHERNET MAC 10-PORT 552-BGA
Manufacturer
Cortina Systems Inc
Specifications of WFIXF1110CC.B3-998845
Controller Type
Ethernet Controller, MAC
Interface
SPI-4.2
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
575-BCBGA Exposed Pad (552 Bumps)
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
1008-1037
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
WFIXF1110CC.B3-998845
Manufacturer:
Maxim
Quantity:
43
Company:
Part Number:
WFIXF1110CC.B3-998845
Manufacturer:
Cortina Systems Inc
Quantity:
10 000
IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 96
Cortina Systems
TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D) (Sheet 2 of 2)
®
TX FIFO MAC
Transfer
Threshold Port 5
TX FIFO MAC
Transfer
Threshold Port 6
TX FIFO MAC
Transfer
Threshold Port 7
TX FIFO MAC
Transfer
Threshold Port 8
TX FIFO MAC
Transfer
Threshold Port 9
1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write
2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9):
3. For proper operation of the IXF1110 MAC, the MAC transfer threshold must be set to greater than the
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Bits 31:13 - Reserved and R.
Bits 12:0 - Described above.
MaxBurst1 on the SPI4-2.
Name
2
Description
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to MAC. The bottom 3 bits of this
register are ignored, thus the threshold is set in
increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, thus the threshold is
set in increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
Sets the value at which the FIFO begins to
transfer data to the MAC. The bottom 3 bits of
this register are ignored, thus the threshold is
set in increments of 8 byte steps.
If this register is set above the standard packet
size (including the 8-byte round-up), full packet
transfers from the FIFO only are allowed.
Transfer begins when either the count value in
this register is exceeded or an End-of-Frame is
received.
3
Address
0x61C
0x61D
0x61A
0x61B
0x619
Type
R/W
R/W
R/W
R/W
R/W
1
8.5 Memory Map
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
Default
Page 158