EFM32G890F64 Energy Micro, EFM32G890F64 Datasheet - Page 72

• Manufacturer Part Number: EFM32G890F64
• Description: MCU 32BIT 64KB FLASH 112-BGA
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G890F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LFBGA
• Processor Series: EFM32G890
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.7.21 DMA_IEN - Interrupt Enable register
8.7.22 DMA_CHx_CTRL - Channel Control Register
31
30:8
7
6
5
4
3
2
1
0
31:22
21:16
Offset
0x100C
Reset
Access
Name
Bit
Offset
0x1100
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
ERR
Set this bit to enable interrupt on AHB bus error.
Reserved
CH7DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH6DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH5DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH4DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH3DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH2DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH1DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH0DONE
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
Reserved
SOURCESEL
Select input source to DMA channel.
Name
Name
0
0
0
0
0
0
0
0
0
0x00
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
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Bit Position
Bit Position
72
DMA Error Interrupt Flag Enable
DMA Channel 7 Complete Interrupt Enable
DMA Channel 6 Complete Interrupt Enable
DMA Channel 5 Complete Interrupt Enable
DMA Channel 4 Complete Interrupt Enable
DMA Channel 3 Complete Interrupt Enable
DMA Channel 2 Complete Interrupt Enable
DMA Channel 1 Complete Interrupt Enable
DMA Channel 0 Complete Interrupt Enable
Source Select
Description
Description
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