ATMEGA64L-8AQR Atmel, ATMEGA64L-8AQR Datasheet - Page 253
ATMEGA64L-8AQR
Manufacturer Part Number
ATMEGA64L-8AQR
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8AQR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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On-chip Debug
Related Register in
I/O Memory
OCDR – On-chip
Debug Register
Using the JTAG
Programming
Capabilities
Bibliography
2490Q–AVR–06/10
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUSR Register must be cleared to enable the
JTAG Test Access Port.
The JTAG programming capability supports:
•
•
•
•
The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a Chip Erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section
For more information about general Boundary-scan, the following literature can be consulted:
•
•
Bit
0x22 (0x42)
Read/Write
Initial Value
Flash Programming and verifying
EEPROM Programming and verifying
Fuse Programming and verifying
Lock bit Programming and verifying
IEEE: IEEE Std 1149.1 - 1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison –Wesley,
1992.
MSB/IDRD
R/W
7
0
R/W
6
0
R/W
5
0
“Programming Via the JTAG Interface” on page
R/W
4
0
R/W
3
0
R/W
2
0
R/W
0
1
ATmega64(L)
LSB
R/W
0
0
OCDR
311.
253
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