ATMEGA64L-8MU Atmel, ATMEGA64L-8MU Datasheet

IC AVR MCU 64K 8MHZ 3V 64-QFN

ATMEGA64L-8MU

Manufacturer Part Number
ATMEGA64L-8MU
Description
IC AVR MCU 64K 8MHZ 3V 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64L-8MU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
JTAG/SPI/TWI/USART
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
MLF EP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Package
64MLF EP
Family Name
ATmega
Maximum Speed
8 MHz
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64L-8MU
Quantity:
113
Part Number:
ATMEGA64L-8MUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 64 Kbytes of In-System Reprogrammable Flash program memory
– 2 Kbytes EEPROM
– 4 Kbytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64 Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
– 2.7V - 5.5V for ATmega64L
– 4.5V - 5.5V for ATmega64
– 0 - 8 MHz for ATmega64L
– 0 - 16 MHz for ATmega64
True Read-While-Write Operation
Capture Mode
and Extended Standby
In-System Programming by On-chip Boot Program
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain (1x, 10x, 200x)
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 64K Bytes
In-System
Programmable
Flash
ATmega64
ATmega64L
Summary
2490QS–AVR–07/10

Related parts for ATMEGA64L-8MU

ATMEGA64L-8MU Summary of contents

Page 1

... Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V for ATmega64L – 4.5V - 5.5V for ATmega64 • Speed Grades – MHz for ATmega64L – MHz for ATmega64 ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller ...

Page 2

Pin Configuration Figure 1. Pinout ATmega64 PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Disclaimer Typical ...

Page 3

Overview The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize ...

Page 4

... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega64 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits ...

Page 5

ATmega103 By programming the M103C Fuse, the ATmega64 will be compatible with the ATmega103 Compatibility Mode regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new fea- tures in ATmega64 are not available in this compatibility ...

Page 6

Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins ...

Page 7

RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in 52. Shorter pulses are not guaranteed ...

Page 8

... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATmega64( ...

Page 9

Register Summary Address Name Bit 7 (0xFF) Reserved – .. Reserved – (0x9E) Reserved – (0x9D) UCSR1C – (0x9C) UDR1 (0x9B) UCSR1A RXC1 (0x9A) UCSR1B RXCIE1 (0x99) UBRR1L (0x98) UBRR1H – (0x97) Reserved – (0x96) Reserved – (0x95) UCSR0C – ...

Page 10

Register Summary (Continued) Address Name Bit 7 (0x60) Reserved – 0x3F (0x5F) SREG I 0x3E (0x5E) SPH SP15 0x3D (0x5D) SPL SP7 0x3C (0x5C) XDIV XDIVEN 0x3B (0x5B) Reserved – 0x3A (0x5A) EICRB ISC71 0x39 (0x59) EIMSK INT7 0x38 (0x58) ...

Page 11

Register Summary (Continued) Address Name Bit 7 0x00 (0x20) PINF PINF7 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status ...

Page 12

Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...

Page 13

Instruction Set Summary (Continued) BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate LD Rd, X Load ...

Page 14

Instruction Set Summary (Continued) CLH Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega64( ← None (see specific descr. for Sleep function) None (see specific ...

Page 15

... Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 × 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2490QS–AVR–07/10 (2) (1) Ordering Code Package ATmega64L-8AU 64A ATmega64L-8MU 64M1 ATmega64-16AU 64A ATmega64-16MU 64M1 Package Type ATmega64(L) Operation Range Industrial ° ...

Page 16

Packaging Information 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...

Page 17

Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R 2490QS–AVR–07/10 ...

Page 18

Errata The revision letter in this section refers to the revision of the ATmega64 device. ATmega64, rev. A • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer ...

Page 19

Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL reg- ister, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior ...

Page 20

Datasheet Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Revision History Changes from Rev. 1. Changed “Low” into “Ext” in 2490P-07/09 ...

Page 21

Changes from Rev. 1. Updated 2490J-03/ Added Rev. 2490K-04/06 3. Added Addresses in Register Descriptions. 4. Updated 5. Updated Register- and bit names in 6. Updated note in 7. Updated Features in Changes from Rev. 1. MLF-package alternative ...

Page 22

Changes from Rev. 2490F-12/03 to Rev. 2490G-03/04 Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03 Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03 ATmega64(L) 22 12. Updated features in“Analog to Digital Converter” on page 230 ...

Page 23

Added section 11. Changed V 12. Added information about conversion time for Differential mode with Auto Triggering on 13. Added t 14. Updated Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. 2490B-09/02 to ...

Page 24

In the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of “OSCCAL – Oscillator Calibration Register(1)” ...

Page 25

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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