ATMEGA64L-8AQR Atmel, ATMEGA64L-8AQR Datasheet - Page 122
ATMEGA64L-8AQR
Manufacturer Part Number
ATMEGA64L-8AQR
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8AQR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Force Output
Compare
Compare Match
Blocking by TCNTn
Write
Using the Output
Compare Unit
Compare Match
Output Unit
2490Q–AVR–06/10
automatically as the TCNTn – and ICRn Register). Therefore OCRnx is not read via the high
byte temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCRnx registers must be done via the TEMP Regis-
ter since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper eight bits of either the OCRnx Buffer or OCRnx Com-
pare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to
on page
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare Match will not set the
OCFnx flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare
Match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or
toggled).
All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the
same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
Since writing TCNTn in any mode of operation will block all Compare Matches for one timer
clock cycle, there are risks involved when changing TCNTn when using any of the Output Com-
pare channels, independent of whether the Timer/Counter is running or not. If the value written
to TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect
waveform generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP
values. The Compare Match for the TOP will be ignored and the counter will continue to
0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is
downcounting.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com-
pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between waveform generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses
the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next Compare Match.
Secondly the COMnx1:0 bits control the OCnx pin output source.
schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR
and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx
state, the reference is for the internal OCnx Register, not the OCnx pin. If a System Reset occur,
the OCnx Register is reset to “0”.
115.
Figure 50
“Accessing 16-bit Registers”
ATmega64(L)
shows a simplified
122
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